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| author | Craig Topper <craig.topper@intel.com> | 2017-11-18 18:49:16 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-11-18 18:49:16 +0000 |
| commit | 410bbcdcf19864068e6849e49917ff529710859c (patch) | |
| tree | c39696e80f29e1942709128ffc0bc293d7918872 /llvm/lib | |
| parent | c9bc55a08d62c64ae478a1c4ac58087ac2f597bd (diff) | |
| download | bcm5719-llvm-410bbcdcf19864068e6849e49917ff529710859c.tar.gz bcm5719-llvm-410bbcdcf19864068e6849e49917ff529710859c.zip | |
[X86] Qualify a few places with ExperimentalVectorWideningLegalization.
I'm playing around with this flag and these places cause errors if not qualified.
llvm-svn: 318595
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index f5daec99c83..da30be53fa1 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -24602,8 +24602,10 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops); SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1); - Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res, - DAG.getIntPtrConstant(0, dl))); + if (!ExperimentalVectorWideningLegalization) + Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res, + DAG.getIntPtrConstant(0, dl)); + Results.push_back(Res); return; } // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32. @@ -24645,7 +24647,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, SDValue Res = DAG.getNode(IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI, dl, MVT::v4i32, Src); - Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i32, Res, Idx); + if (!ExperimentalVectorWideningLegalization) + Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i32, Res, Idx); Results.push_back(Res); return; } @@ -24655,7 +24658,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, DAG.getUNDEF(MVT::v2f32)); Res = DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, dl, MVT::v4i32, Res); - Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i32, Res, Idx); + if (!ExperimentalVectorWideningLegalization) + Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i32, Res, Idx); Results.push_back(Res); return; } |
