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authorNate Begeman <natebegeman@mac.com>2005-12-14 00:34:09 +0000
committerNate Begeman <natebegeman@mac.com>2005-12-14 00:34:09 +0000
commit40f081d8e08ceed3611be3dd2809741b6047f334 (patch)
treea037a019941f8692de2e460586c14f5d7f94cf91 /llvm/lib
parent69caef2b781130a7d0eeaf8898eb346b6423ae03 (diff)
downloadbcm5719-llvm-40f081d8e08ceed3611be3dd2809741b6047f334.tar.gz
bcm5719-llvm-40f081d8e08ceed3611be3dd2809741b6047f334.zip
Add support for fmul node of type v4f32.
void %foo(<4 x float> * %a) { entry: %tmp1 = load <4 x float> * %a; %tmp2 = mul <4 x float> %tmp1, %tmp1 store <4 x float> %tmp2, <4 x float> *%a ret void } Is selected to: _foo: li r2, 0 lvx v0, r2, r3 vxor v1, v1, v1 vmaddfp v0, v0, v0, v1 stvx v0, r2, r3 blr llvm-svn: 24701
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrFormats.td8
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td13
2 files changed, 21 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index 96c969b4d0a..8b28e5f8145 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -602,6 +602,14 @@ class VXForm_1<bits<11> xo, dag OL, string asmstr,
let Inst{21-31} = xo;
}
+class VXForm_setzero<bits<11> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : VXForm_1<xo, OL, asmstr, itin, pattern> {
+ let VA = VD;
+ let VB = VD;
+}
+
+
class VXForm_2<bits<11> xo, dag OL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<4, OL, asmstr, itin> {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 3ea09202899..1a30985975c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -897,6 +897,16 @@ def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
"vsubfp $vD, $vA, $vB", VecFP,
[(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
+def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vxor $vD, $vA, $vB", VecFP,
+ []>;
+
+// VX-Form Pseudo Instructions
+
+def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
+ "vxor $vD, $vD, $vD", VecFP,
+ []>;
+
//===----------------------------------------------------------------------===//
// PowerPC Instruction Patterns
@@ -951,6 +961,9 @@ def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
(ADDIS GPRC:$in, tconstpool:$g)>;
+def : Pat<(fmul VRRC:$vA, VRRC:$vB),
+ (VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>;
+
// Fused multiply add and multiply sub for packed float. These are represented
// separately from the real instructions above, for operations that must have
// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
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