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| author | Evgenii Stepanov <eugenis@google.com> | 2019-12-09 16:52:31 -0800 |
|---|---|---|
| committer | Evgenii Stepanov <eugenis@google.com> | 2020-01-06 11:48:35 -0800 |
| commit | 40a80a0a19f4ed1b5d4a2e842c5541da36342c14 (patch) | |
| tree | 9422fdf6ad979f8c4a1f4467d6ff7541ce776f2c /llvm/lib | |
| parent | df3f4e0d77e53193acd423d1b02d3fd3bf065bf7 (diff) | |
| download | bcm5719-llvm-40a80a0a19f4ed1b5d4a2e842c5541da36342c14.tar.gz bcm5719-llvm-40a80a0a19f4ed1b5d4a2e842c5541da36342c14.zip | |
Lower TAGPstack with negative offset to SUBG.
Summary:
This never really occurs in the current codegen, so only a MIR test is
possible.
Reviewers: ostannard, pcc
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72123
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 9 |
2 files changed, 12 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp index 09a525d4b06..3b8f8a19fe4 100644 --- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp @@ -696,10 +696,12 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB, return true; } case AArch64::TAGPstack: { - BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDG)) + int64_t Offset = MI.getOperand(2).getImm(); + BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(Offset >= 0 ? AArch64::ADDG : AArch64::SUBG)) .add(MI.getOperand(0)) .add(MI.getOperand(1)) - .add(MI.getOperand(2)) + .addImm(std::abs(Offset)) .add(MI.getOperand(4)); MI.eraseFromParent(); return true; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 45a2d77c111..abde3e50021 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -2188,12 +2188,19 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, unsigned &Scale, MaxOffset = 4095; break; case AArch64::ADDG: - case AArch64::TAGPstack: Scale = 16; Width = 0; MinOffset = 0; MaxOffset = 63; break; + case AArch64::TAGPstack: + Scale = 16; + Width = 0; + // TAGP with a negative offset turns into SUBP, which has a maximum offset + // of 63 (not 64!). + MinOffset = -63; + MaxOffset = 63; + break; case AArch64::LDG: case AArch64::STGOffset: case AArch64::STZGOffset: |
