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| author | Simon Tatham <simon.tatham@arm.com> | 2019-12-06 15:23:07 +0000 |
|---|---|---|
| committer | Simon Tatham <simon.tatham@arm.com> | 2019-12-06 15:23:23 +0000 |
| commit | 3fab4276cbf1a57f049428145d4c9a0d9bcfa82c (patch) | |
| tree | 87d0b708268295d2c9812a9ddbe1a8b555f66763 /llvm/lib | |
| parent | 4a7e00df346561131a07db350643ec54113129a1 (diff) | |
| download | bcm5719-llvm-3fab4276cbf1a57f049428145d4c9a0d9bcfa82c.tar.gz bcm5719-llvm-3fab4276cbf1a57f049428145d4c9a0d9bcfa82c.zip | |
[ARM][MVE] Fix copy-paste error in VQSHL instruction ids.
Summary:
The immediate forms of the MVE VQSHL instruction have MC names like
`MVE_VSLIimms8` and `MVE_VSLIimmu32`. Those names are confusing,
because VSLI is a completely different shift instruction with no
semantic relation to VQSHL. But it just happens to be defined
immediately before VQSHL in `ARMInstrMVE.td`, so this looks like a
copy-paste error. Renamed the ids to match the instruction name.
Reviewers: ostannard, dmgreen, MarkMurrayARM, miyuki
Reviewed By: miyuki
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71114
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrMVE.td | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td index c81e60b3360..3c0499ac490 100644 --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -2529,32 +2529,32 @@ class MVE_VQSHL_imm<string suffix, dag imm> let Inst{10-8} = 0b111; } -def MVE_VSLIimms8 : MVE_VQSHL_imm<"s8", (ins imm0_7:$imm)> { +def MVE_VQSHLimms8 : MVE_VQSHL_imm<"s8", (ins imm0_7:$imm)> { let Inst{28} = 0b0; let Inst{21-19} = 0b001; } -def MVE_VSLIimmu8 : MVE_VQSHL_imm<"u8", (ins imm0_7:$imm)> { +def MVE_VQSHLimmu8 : MVE_VQSHL_imm<"u8", (ins imm0_7:$imm)> { let Inst{28} = 0b1; let Inst{21-19} = 0b001; } -def MVE_VSLIimms16 : MVE_VQSHL_imm<"s16", (ins imm0_15:$imm)> { +def MVE_VQSHLimms16 : MVE_VQSHL_imm<"s16", (ins imm0_15:$imm)> { let Inst{28} = 0b0; let Inst{21-20} = 0b01; } -def MVE_VSLIimmu16 : MVE_VQSHL_imm<"u16", (ins imm0_15:$imm)> { +def MVE_VQSHLimmu16 : MVE_VQSHL_imm<"u16", (ins imm0_15:$imm)> { let Inst{28} = 0b1; let Inst{21-20} = 0b01; } -def MVE_VSLIimms32 : MVE_VQSHL_imm<"s32", (ins imm0_31:$imm)> { +def MVE_VQSHLimms32 : MVE_VQSHL_imm<"s32", (ins imm0_31:$imm)> { let Inst{28} = 0b0; let Inst{21} = 0b1; } -def MVE_VSLIimmu32 : MVE_VQSHL_imm<"u32", (ins imm0_31:$imm)> { +def MVE_VQSHLimmu32 : MVE_VQSHL_imm<"u32", (ins imm0_31:$imm)> { let Inst{28} = 0b1; let Inst{21} = 0b1; } |
