diff options
| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-08-01 16:47:48 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-08-01 16:47:48 +0000 |
| commit | 3f24ff61300afb16d04dcf6403cbe10826aab67e (patch) | |
| tree | b6d363ba51e48ca3587bbcb514761b6f1b4baf49 /llvm/lib | |
| parent | e2cc5892832436d0307cea4ab4dcde26211354a4 (diff) | |
| download | bcm5719-llvm-3f24ff61300afb16d04dcf6403cbe10826aab67e.tar.gz bcm5719-llvm-3f24ff61300afb16d04dcf6403cbe10826aab67e.zip | |
[X86][SSE] Added missing PACKSS/PACKUS intrinsic schedules
Improves atom scheduler test coverage (to make it easier to upgrade them for PR32431).
Checked on Agner that these actually match the UNPACK schedules, but better to include a separate class
llvm-svn: 309701
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86Schedule.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleAtom.td | 1 |
3 files changed, 10 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index c7305aec9a8..b3c5ae54181 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -4249,8 +4249,8 @@ multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT, !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), [(set VR128:$dst, - (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>, - Sched<[WriteShuffle]>; + (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))], + IIC_SSE_PACK>, Sched<[WriteShuffle]>; def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), !if(Is2Addr, @@ -4259,8 +4259,8 @@ multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), [(set VR128:$dst, (OutVT (OpNode (ArgVT VR128:$src1), - (bitconvert (ld_frag addr:$src2)))))]>, - Sched<[WriteShuffleLd, ReadAfterLd]>; + (bitconvert (ld_frag addr:$src2)))))], + IIC_SSE_PACK>, Sched<[WriteShuffleLd, ReadAfterLd]>; } multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT, @@ -4292,8 +4292,8 @@ multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT, !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), [(set VR128:$dst, - (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>, - Sched<[WriteShuffle]>; + (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))], + IIC_SSE_PACK>, Sched<[WriteShuffle]>; def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), !if(Is2Addr, @@ -4302,8 +4302,8 @@ multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), [(set VR128:$dst, (OutVT (OpNode (ArgVT VR128:$src1), - (bitconvert (ld_frag addr:$src2)))))]>, - Sched<[WriteShuffleLd, ReadAfterLd]>; + (bitconvert (ld_frag addr:$src2)))))], + IIC_SSE_PACK>, Sched<[WriteShuffleLd, ReadAfterLd]>; } multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT, diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td index d831a797435..64662e8d18e 100644 --- a/llvm/lib/Target/X86/X86Schedule.td +++ b/llvm/lib/Target/X86/X86Schedule.td @@ -299,6 +299,7 @@ def IIC_SSE_SHUFP : InstrItinClass; def IIC_SSE_PSHUF_RI : InstrItinClass; def IIC_SSE_PSHUF_MI : InstrItinClass; +def IIC_SSE_PACK : InstrItinClass; def IIC_SSE_UNPCK : InstrItinClass; def IIC_SSE_MOVMSK : InstrItinClass; diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td index a5b440182aa..200a3216f6f 100644 --- a/llvm/lib/Target/X86/X86ScheduleAtom.td +++ b/llvm/lib/Target/X86/X86ScheduleAtom.td @@ -212,6 +212,7 @@ def AtomItineraries : ProcessorItineraries< InstrItinData<IIC_SSE_PSHUF_RI, [InstrStage<1, [Port0]>] >, InstrItinData<IIC_SSE_PSHUF_MI, [InstrStage<1, [Port0]>] >, + InstrItinData<IIC_SSE_PACK, [InstrStage<1, [Port0]>] >, InstrItinData<IIC_SSE_UNPCK, [InstrStage<1, [Port0]>] >, InstrItinData<IIC_SSE_SQRTPS_RR, [InstrStage<70, [Port0, Port1]>] >, |
