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| author | Craig Topper <craig.topper@intel.com> | 2018-09-23 06:49:47 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-09-23 06:49:47 +0000 |
| commit | 3e0b4b0eb7575654b34e67aff7452cab3c85d82d (patch) | |
| tree | ca0da10e9314838e1291434f72821ebc1a820d65 /llvm/lib | |
| parent | 72d195ecf03b5ed9622fd16e36be053b3664e499 (diff) | |
| download | bcm5719-llvm-3e0b4b0eb7575654b34e67aff7452cab3c85d82d.tar.gz bcm5719-llvm-3e0b4b0eb7575654b34e67aff7452cab3c85d82d.zip | |
[X86] Fix a few typos in comments.
llvm-svn: 342829
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 67d93fa9500..398bf11065c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -17308,7 +17308,7 @@ static SDValue LowerZERO_EXTEND_Mask(SDValue Op, SDLoc DL(Op); unsigned NumElts = VT.getVectorNumElements(); - // For all vectors, but vXi8 we can just emit a sign_extend a shift. This + // For all vectors, but vXi8 we can just emit a sign_extend and a shift. This // avoids a constant pool load. if (VT.getVectorElementType() != MVT::i8) { SDValue Extend = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, In); @@ -19520,7 +19520,7 @@ static SDValue LowerSIGN_EXTEND_Mask(SDValue Op, unsigned NumElts = VT.getVectorNumElements(); - // Extend VT if the scalar type is v8/v16 and BWI is not supported. + // Extend VT if the scalar type is i8/i16 and BWI is not supported. MVT ExtVT = VT; if (!Subtarget.hasBWI() && VTElt.getSizeInBits() <= 16) { // If v16i32 is to be avoided, we'll need to split and concatenate. |
