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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-01-29 11:28:06 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-01-29 11:28:06 +0000 |
| commit | 3ddb7fb6637242cfd871ef22ea240d3669e61c34 (patch) | |
| tree | 5f268c30481ba84f5a87b4217118034528a99b25 /llvm/lib | |
| parent | 02d4e50e9d68953ef718c9603774dba064bb2de3 (diff) | |
| download | bcm5719-llvm-3ddb7fb6637242cfd871ef22ea240d3669e61c34.tar.gz bcm5719-llvm-3ddb7fb6637242cfd871ef22ea240d3669e61c34.zip | |
[ARM] FP16Pat and FullFP16Pat patterns. NFC.
Create and use FP16Pat FullFP16Pat helper patterns to make the difference
explicit.
Differential Revision: https://reviews.llvm.org/D42634
llvm-svn: 323640
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrFormats.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrVFP.td | 20 |
2 files changed, 16 insertions, 10 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td index 7b90e960f53..70aded247f6 100644 --- a/llvm/lib/Target/ARM/ARMInstrFormats.td +++ b/llvm/lib/Target/ARM/ARMInstrFormats.td @@ -1024,6 +1024,12 @@ class Thumb2DSPPat<dag pattern, dag result> : Pat<pattern, result> { class Thumb2DSPMulPat<dag pattern, dag result> : Pat<pattern, result> { list<Predicate> Predicates = [IsThumb2, UseMulOps, HasDSP]; } +class FP16Pat<dag pattern, dag result> : Pat<pattern, result> { + list<Predicate> Predicates = [HasFP16]; +} +class FullFP16Pat<dag pattern, dag result> : Pat<pattern, result> { + list<Predicate> Predicates = [HasFullFP16]; +} //===----------------------------------------------------------------------===// // Thumb Instruction Format Definitions. // diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index cf558b533af..bfc6cd57fc6 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -674,8 +674,8 @@ def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), Requires<[HasFP16]>, Sched<[WriteFPCVT]>; -def : Pat<(f32 (fpextend HPR:$Sm)), - (VCVTBHS (COPY_TO_REGCLASS HPR:$Sm, SPR))>; +def : FullFP16Pat<(f32 (fpextend HPR:$Sm)), + (VCVTBHS (COPY_TO_REGCLASS HPR:$Sm, SPR))>; def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", @@ -750,17 +750,17 @@ def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0, let Inst{5} = Dm{4}; } -def : Pat<(fp_to_f16 SPR:$a), - (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; +def : FP16Pat<(fp_to_f16 SPR:$a), + (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; -def : Pat<(fp_to_f16 (f64 DPR:$a)), - (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>; +def : FP16Pat<(fp_to_f16 (f64 DPR:$a)), + (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>; -def : Pat<(f16_to_fp GPR:$a), - (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; +def : FP16Pat<(f16_to_fp GPR:$a), + (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; -def : Pat<(f64 (f16_to_fp GPR:$a)), - (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>; +def : FP16Pat<(f64 (f16_to_fp GPR:$a)), + (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>; multiclass vcvt_inst<string opc, bits<2> rm, SDPatternOperator node = null_frag> { |
