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| author | David Spickett <david.spickett@arm.com> | 2019-04-01 14:56:37 +0000 |
|---|---|---|
| committer | David Spickett <david.spickett@arm.com> | 2019-04-01 14:56:37 +0000 |
| commit | 3d233d5d4d82e8d3c6dfd39367dfaf9587c2107b (patch) | |
| tree | 50ac1563fa9ec9d63e3e8fa1ce3e65866136b733 /llvm/lib | |
| parent | 44668ae7c7df73ca255a688e534af49ac9600323 (diff) | |
| download | bcm5719-llvm-3d233d5d4d82e8d3c6dfd39367dfaf9587c2107b.tar.gz bcm5719-llvm-3d233d5d4d82e8d3c6dfd39367dfaf9587c2107b.zip | |
[AArch64] Add v8.5-a Memory Tagging STZGM instruction
This instruction writes a block of allocation tags
and stores zero to the associated data locations.
It differs from STGM by 1 bit and has the same
arguments.
The specification can be found here:
https://developer.arm.com/docs/ddi0596/c
Differential Revision: https://reviews.llvm.org/D60065
llvm-svn: 357397
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 347f0104c35..ee496fa5d43 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -1261,6 +1261,10 @@ def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]", def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]", (outs), (ins GPR64:$Rt, GPR64sp:$Rn)>; +def STZGM : MemTagVector<0, "stzgm", "\t$Rt, [$Rn]", + (outs), (ins GPR64:$Rt, GPR64sp:$Rn)> { + let Inst{23} = 0; +} defm STG : MemTagStore<0b00, "stg">; defm STZG : MemTagStore<0b01, "stzg">; |
