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| author | Jan Vesely <jan.vesely@rutgers.edu> | 2016-06-25 18:24:16 +0000 |
|---|---|---|
| committer | Jan Vesely <jan.vesely@rutgers.edu> | 2016-06-25 18:24:16 +0000 |
| commit | 3bc1af2be470106c961fdae4d08fdbe444a2114d (patch) | |
| tree | 3399f400d007cbb53cbaf59d34e401c8a92c4ffb /llvm/lib | |
| parent | 51ff79fd82a307d8476d792630a990c4d8b3a0bf (diff) | |
| download | bcm5719-llvm-3bc1af2be470106c961fdae4d08fdbe444a2114d.tar.gz bcm5719-llvm-3bc1af2be470106c961fdae4d08fdbe444a2114d.zip | |
AMDGPU/R600: Fix GlobalValue regressions.
Don't cast GV expression to MCSymbolRefExpr. r272705 changed GV to binary
expressions by including offset even if the offset it 0
(we haven't hit this sooner since tested workloads don't include static offsets)
We don't really care about the type of expression, so set it directly.
Fixes: r272705
Consider section relative relocations. Since all const as data is in one boffer section relative is equivalent to abs32.
Fixes: r273166
Differential Revision: http://reviews.llvm.org/D21633
llvm-svn: 273785
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp index 6031522b0d6..b4e3b8e896b 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp @@ -56,6 +56,8 @@ unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx, default: break; case FK_PCRel_4: return ELF::R_AMDGPU_REL32; + case FK_SecRel_4: + return ELF::R_AMDGPU_ABS32; } llvm_unreachable("unhandled relocation type"); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp index 381ef011cac..5e8e6ceb7ca 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp @@ -163,7 +163,6 @@ uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, } if (MO.isExpr()) { - const MCSymbolRefExpr *Expr = cast<MCSymbolRefExpr>(MO.getExpr()); // We put rodata at the end of code section, then map the entire // code secetion as vtx buf. Thus the section relative address is the // correct one. @@ -171,7 +170,7 @@ uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, // We can't easily get the order of the current one, so compare against // the first one and adjust offset. const unsigned offset = (&MO == &MI.getOperand(0)) ? 0 : 4; - Fixups.push_back(MCFixup::create(offset, Expr, FK_SecRel_4, MI.getLoc())); + Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4, MI.getLoc())); return 0; } |

