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author | Elad Cohen <elad2.cohen@intel.com> | 2017-08-14 09:06:00 +0000 |
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committer | Elad Cohen <elad2.cohen@intel.com> | 2017-08-14 09:06:00 +0000 |
commit | 3a90a0c10d64ceccad57af8dfc7c049f4cb0abae (patch) | |
tree | bf01374406cea39ad22a02137d064116923d994e /llvm/lib | |
parent | db8b2d7b203a8de5c67f6703d3a5cfb211a6a755 (diff) | |
download | bcm5719-llvm-3a90a0c10d64ceccad57af8dfc7c049f4cb0abae.tar.gz bcm5719-llvm-3a90a0c10d64ceccad57af8dfc7c049f4cb0abae.zip |
Revert "[DAGCombiner] Extending pattern detection for vector shuffle (REAPPLIED)"
This reverts commit r310782.
llvm-svn: 310822
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 49 |
1 files changed, 2 insertions, 47 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index d2973e5a832..88dc0f4bde6 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -14186,18 +14186,10 @@ SDValue DAGCombiner::createBuildVecShuffle(const SDLoc &DL, SDNode *N, EVT InVT1 = VecIn1.getValueType(); EVT InVT2 = VecIn2.getNode() ? VecIn2.getValueType() : InVT1; - unsigned Vec2Offset = 0; + unsigned Vec2Offset = InVT1.getVectorNumElements(); unsigned NumElems = VT.getVectorNumElements(); unsigned ShuffleNumElems = NumElems; - // In case both the input vectors are extracted from same base - // vector we do not need extra addend (Vec2Offset) while - // computing shuffle mask. - if (!VecIn2 || !(VecIn1.getOpcode() == ISD::EXTRACT_SUBVECTOR) || - !(VecIn2.getOpcode() == ISD::EXTRACT_SUBVECTOR) || - !(VecIn1.getOperand(0) == VecIn2.getOperand(0))) - Vec2Offset = InVT1.getVectorNumElements(); - // We can't generate a shuffle node with mismatched input and output types. // Try to make the types match the type of the output. if (InVT1 != VT || InVT2 != VT) { @@ -14344,6 +14336,7 @@ SDValue DAGCombiner::reduceBuildVecToShuffle(SDNode *N) { if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || !isa<ConstantSDNode>(Op.getOperand(1))) return SDValue(); + SDValue ExtractedFromVec = Op.getOperand(0); // All inputs must have the same element type as the output. @@ -14366,44 +14359,6 @@ SDValue DAGCombiner::reduceBuildVecToShuffle(SDNode *N) { if (VecIn.size() < 2) return SDValue(); - // If all the Operands of BUILD_VECTOR extract from same - // vector, then split the vector efficiently based on the maximum - // vector access index and adjust the VectorMask and - // VecIn accordingly. - if (VecIn.size() == 2) { - unsigned MaxIndex = 0; - unsigned NearestPow2 = 0; - SDValue Vec = VecIn.back(); - EVT InVT = Vec.getValueType(); - MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout()); - SmallVector<unsigned, 8> IndexVec(NumElems, 0); - - for (unsigned i = 0; i < NumElems; i++) { - if (VectorMask[i] <= 0) - continue; - unsigned Index = N->getOperand(i).getConstantOperandVal(1); - IndexVec[i] = Index; - MaxIndex = std::max(MaxIndex, Index); - } - - NearestPow2 = PowerOf2Ceil(MaxIndex); - if (InVT.isSimple() && (NearestPow2 > 2) && ((NumElems * 2) < NearestPow2)) { - unsigned SplitSize = NearestPow2 / 2; - EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), - InVT.getVectorElementType(), SplitSize); - SDValue VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec, - DAG.getConstant(SplitSize, DL, IdxTy)); - SDValue VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, Vec, - DAG.getConstant(0, DL, IdxTy)); - VecIn.pop_back(); - VecIn.push_back(VecIn1); - VecIn.push_back(VecIn2); - - for (unsigned i = 0; i < NumElems; i++) - VectorMask[i] = (IndexVec[i] < SplitSize) ? 1 : 2; - } - } - // TODO: We want to sort the vectors by descending length, so that adjacent // pairs have similar length, and the longer vector is always first in the // pair. |