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| author | Chris Lattner <sabre@nondot.org> | 2006-03-25 07:36:56 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-03-25 07:36:56 +0000 |
| commit | 3a66a75108e46bc5e63698d6993d14a4123908dd (patch) | |
| tree | 21a46ae2a9bdcb5e2c4172dcbbe30608be759327 /llvm/lib | |
| parent | 0fcb446a786db8213e88ba4bbe05c1b7e9cafd9e (diff) | |
| download | bcm5719-llvm-3a66a75108e46bc5e63698d6993d14a4123908dd.tar.gz bcm5719-llvm-3a66a75108e46bc5e63698d6993d14a4123908dd.zip | |
add all supported formats to the vector register file
llvm-svn: 27115
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index fe5c9d351ef..4f56cf74e54 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -259,7 +259,7 @@ def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; -def VRRC : RegisterClass<"PPC", [v16i8,v4f32,v4i32], 128, +def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128, [V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>; |
