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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-11-18 20:09:55 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-11-18 20:09:55 +0000 |
| commit | 3a4d86a1a4790299afd1a96e6eac04083ad80e63 (patch) | |
| tree | 8fc69f2ff214acb00d96b3509580040b2a8a3516 /llvm/lib | |
| parent | 08f7e37aa992b2e277e2b29b3bc1d9b4b6fec2e8 (diff) | |
| download | bcm5719-llvm-3a4d86a1a4790299afd1a96e6eac04083ad80e63.tar.gz bcm5719-llvm-3a4d86a1a4790299afd1a96e6eac04083ad80e63.zip | |
R600/SI: Fix moveToVALU when the first operand is VSrc.
Moving into a VSrc doesn't always work, since it could be
replaced with an SGPR later.
llvm-svn: 195042
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstrInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIRegisterInfo.cpp | 2 |
2 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.cpp b/llvm/lib/Target/R600/SIInstrInfo.cpp index 7f23ecf91f3..ab55c1b173c 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.cpp +++ b/llvm/lib/Target/R600/SIInstrInfo.cpp @@ -417,7 +417,6 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const { MachineOperand &MO = MI->getOperand(OpIdx); MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass; - // XXX - This shouldn't be VSrc const TargetRegisterClass *RC = RI.getRegClass(RCID); unsigned Opcode = AMDGPU::V_MOV_B32_e32; if (MO.isReg()) { @@ -426,7 +425,8 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const { Opcode = AMDGPU::S_MOV_B32; } - unsigned Reg = MRI.createVirtualRegister(RI.getRegClass(RCID)); + const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); + unsigned Reg = MRI.createVirtualRegister(VRC); BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode), Reg).addOperand(MO); MO.ChangeToRegister(Reg, false); diff --git a/llvm/lib/Target/R600/SIRegisterInfo.cpp b/llvm/lib/Target/R600/SIRegisterInfo.cpp index 97c216d3d5b..ed0bbaffae6 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.cpp +++ b/llvm/lib/Target/R600/SIRegisterInfo.cpp @@ -100,6 +100,8 @@ const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass( const TargetRegisterClass *SRC) const { if (hasVGPRs(SRC)) { return SRC; + } else if (SRC == &AMDGPU::SCCRegRegClass) { + return &AMDGPU::VCCRegRegClass; } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) { return &AMDGPU::VReg_32RegClass; } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) { |
