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| author | Chris Lattner <sabre@nondot.org> | 2003-11-07 00:34:33 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2003-11-07 00:34:33 +0000 |
| commit | 395aef6bbeaa51ef9a5c1c6366e52b0b3f26c030 (patch) | |
| tree | 02030058bc57c288fe1bae10c0e70404f4958fd2 /llvm/lib | |
| parent | 6c91a333ea14656b21fd2ae5d9d6c535d1209c27 (diff) | |
| download | bcm5719-llvm-395aef6bbeaa51ef9a5c1c6366e52b0b3f26c030.tar.gz bcm5719-llvm-395aef6bbeaa51ef9a5c1c6366e52b0b3f26c030.zip | |
Hopefully fix the objdir != srcdir issue
llvm-svn: 9761
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/Makefile | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/Makefile b/llvm/lib/Target/X86/Makefile index fa13a93e1e2..b151fa7ecf7 100644 --- a/llvm/lib/Target/X86/Makefile +++ b/llvm/lib/Target/X86/Makefile @@ -15,27 +15,33 @@ $(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \ X86GenRegisterInfo.inc X86GenInstrNames.inc \ X86GenInstrInfo.inc X86GenInstrSelector.inc -X86GenRegisterNames.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN) +X86GenRegisterNames.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \ + $(SourceDir)/../Target.td $(TBLGEN) @echo "Building X86.td register names with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@ -X86GenRegisterInfo.h.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN) +X86GenRegisterInfo.h.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \ + $(SourceDir)/../Target.td $(TBLGEN) @echo "Building X86.td register information header with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@ -X86GenRegisterInfo.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN) +X86GenRegisterInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \ + $(SourceDir)/../Target.td $(TBLGEN) @echo "Building X86.td register information implementation with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@ -X86GenInstrNames.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN) +X86GenInstrNames.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \ + $(SourceDir)/../Target.td $(TBLGEN) @echo "Building X86.td instruction names with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@ -X86GenInstrInfo.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN) +X86GenInstrInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \ + $(SourceDir)/../Target.td $(TBLGEN) @echo "Building X86.td instruction information with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@ -X86GenInstrSelector.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN) +X86GenInstrSelector.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \ + $(SourceDir)/../Target.td $(TBLGEN) @echo "Building X86.td instruction selector with tblgen" $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@ |
