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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-13 16:30:09 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-13 16:55:02 +0000 |
| commit | 38e2c01221a9751c0b797417747200d2e9513b9f (patch) | |
| tree | 1a05964472f8be632189653e90f06ebc69884532 /llvm/lib | |
| parent | 7afaa0099b907842b281c25c2a57937a2c307d3b (diff) | |
| download | bcm5719-llvm-38e2c01221a9751c0b797417747200d2e9513b9f.tar.gz bcm5719-llvm-38e2c01221a9751c0b797417747200d2e9513b9f.zip | |
[SelectionDAG] ComputeNumSignBits add getValidMinimumShiftAmountConstant() ISD::SRA support
Allows us to handle more non-uniform SRA sign bits cases
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 03efc51db2a..54899ab9263 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3608,9 +3608,12 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts, } case ISD::SRA: Tmp = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1); - // SRA X, C -> adds C sign bits. + // SRA X, C -> adds C sign bits. if (const APInt *ShAmt = getValidShiftAmountConstant(Op, DemandedElts)) Tmp = std::min<uint64_t>(Tmp + ShAmt->getZExtValue(), VTBits); + else if (const APInt *ShAmt = + getValidMinimumShiftAmountConstant(Op, DemandedElts)) + Tmp = std::min<uint64_t>(Tmp + ShAmt->getZExtValue(), VTBits); return Tmp; case ISD::SHL: if (const APInt *ShAmt = getValidShiftAmountConstant(Op, DemandedElts)) { |
