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authorColin LeMahieu <colinl@codeaurora.org>2014-11-18 21:51:51 +0000
committerColin LeMahieu <colinl@codeaurora.org>2014-11-18 21:51:51 +0000
commit38765e6d89aa7c83eae34c7ad0cab351a90bc5b6 (patch)
treeafb0279c7508aa61982ea62d90800e764d6482a8 /llvm/lib
parentcc7d7f5e0153ccbffcfdefe55871655541033786 (diff)
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[Hexagon] Adding A2_sub instruction
Renaming test files. llvm-svn: 222263
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.td2
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
index 3acefd5851f..f06c1dcd0b1 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -162,6 +162,7 @@ multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
let isCodeGenOnly = 0 in
defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
+defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
// Pats for instruction selection.
class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
@@ -169,6 +170,7 @@ class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT>
(ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
def: BinOp32_pat<add, A2_add, i32>;
+def: BinOp32_pat<sub, A2_sub, i32>;
multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
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