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| author | Lei Liu <lei.liu2@windriver.com> | 2016-09-29 01:05:48 +0000 |
|---|---|---|
| committer | Lei Liu <lei.liu2@windriver.com> | 2016-09-29 01:05:48 +0000 |
| commit | 361615cfd0ceccd6bc909e16cd81802e04e9c4eb (patch) | |
| tree | 281aa5bee56a1fb92c52127e10502942d1565fd6 /llvm/lib | |
| parent | 790ad869ac05d6d94dc7889f3e65e8bc7320366b (diff) | |
| download | bcm5719-llvm-361615cfd0ceccd6bc909e16cd81802e04e9c4eb.tar.gz bcm5719-llvm-361615cfd0ceccd6bc909e16cd81802e04e9c4eb.zip | |
AArch64: Set shift bit of TLSLE HI12 add instruction
Summary: AArch64 LLVM assembler emits add instruction without shift bit to calculate the higher 12-bit address of TLS variables in local exec model. This generates wrong code sequence to access TLS variables with thread offset larger than 0x1000.
Reviewers: t.p.northover, peter.smith, rovka
Subscribers: salim.nasser, aemerson, llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D24702
llvm-svn: 282661
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp index 5a001c49fb7..e57d39009ee 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp @@ -263,6 +263,14 @@ AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, ++MCNumFixups; + // Set the shift bit of the add instruction for relocation types + // R_AARCH64_TLSLE_ADD_TPREL_HI12 and R_AARCH64_TLSLD_ADD_DTPREL_HI12. + if (const AArch64MCExpr *A64E = dyn_cast<AArch64MCExpr>(Expr)) { + AArch64MCExpr::VariantKind RefKind = A64E->getKind(); + if (RefKind == AArch64MCExpr::VK_TPREL_HI12 || + RefKind == AArch64MCExpr::VK_DTPREL_HI12) + ShiftVal = 12; + } return ShiftVal == 0 ? 0 : (1 << ShiftVal); } |
