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| author | Diana Picus <diana.picus@linaro.org> | 2019-05-09 09:49:36 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2019-05-09 09:49:36 +0000 |
| commit | 3531453371d80c16d21df7815e19d00c8c4f544f (patch) | |
| tree | c52aaae82edebeec109a8a26d698d32044bbb6da /llvm/lib | |
| parent | b1b09e5b55fafe57629878fbdd8cc4b02a9d189e (diff) | |
| download | bcm5719-llvm-3531453371d80c16d21df7815e19d00c8c4f544f.tar.gz bcm5719-llvm-3531453371d80c16d21df7815e19d00c8c4f544f.zip | |
[ARM GlobalISel] Map DBG_VALUE for types != s32
...and make sure we fail elegantly for unsupported values.
s64 goes into DPR, anything <= 32 into GPR.
llvm-svn: 360321
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index 021c13115e3..d03b482043e 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -433,8 +433,14 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { break; case DBG_VALUE: { SmallVector<const ValueMapping *, 4> OperandBanks(NumOperands); - if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg()) - OperandBanks[0] = &ARM::ValueMappings[ARM::GPR3OpsIdx]; + const MachineOperand &MaybeReg = MI.getOperand(0); + if (MaybeReg.isReg() && MaybeReg.getReg()) { + unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); + if (Size > 32 && Size != 64) + return getInvalidInstructionMapping(); + OperandBanks[0] = Size == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] + : &ARM::ValueMappings[ARM::GPR3OpsIdx]; + } OperandsMapping = getOperandsMapping(OperandBanks); break; } |

