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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:13:24 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:13:24 +0000 |
| commit | 34ad780d0defc72e8d880cc2050a66200201227f (patch) | |
| tree | a6725e4e834bba26b47c0f76224cbcde9a367a5a /llvm/lib | |
| parent | 6759661c3f6cfeb4d68a7fb0efa30ec62b28e998 (diff) | |
| download | bcm5719-llvm-34ad780d0defc72e8d880cc2050a66200201227f.tar.gz bcm5719-llvm-34ad780d0defc72e8d880cc2050a66200201227f.zip | |
32 bit shifts have only 12 bit displacements
llvm-svn: 76000
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZOperands.td | 2 |
3 files changed, 15 insertions, 5 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index fb0c5dc42d3..e009eec48b1 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -114,8 +114,11 @@ namespace { #include "SystemZGenDAGISel.inc" private: + bool SelectAddrRI12Only(SDValue Op, SDValue& Addr, + SDValue &Base, SDValue &Disp); bool SelectAddrRI12(SDValue Op, SDValue& Addr, - SDValue &Base, SDValue &Disp); + SDValue &Base, SDValue &Disp, + bool is12BitOnly = false); bool SelectAddrRI(SDValue Op, SDValue& Addr, SDValue &Base, SDValue &Disp); bool SelectAddrRRI12(SDValue Op, SDValue Addr, @@ -346,8 +349,14 @@ void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM, /// Returns true if the address can be represented by a base register plus /// an unsigned 12-bit displacement [r+imm]. +bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue Op, SDValue& Addr, + SDValue &Base, SDValue &Disp) { + return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true); +} + bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr, - SDValue &Base, SDValue &Disp) { + SDValue &Base, SDValue &Disp, + bool is12BitOnly) { SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true); bool Done = false; @@ -373,7 +382,8 @@ bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr, return false; // Check, whether we can match stuff using 20-bit displacements - if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false)) + if (!Done && !is12BitOnly && + !MatchAddress(Addr, AM20, /* is12Bit */ false)) if (AM12.Disp == 0 && AM20.Disp != 0) return false; diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td index 0c0c30bd6d2..8a616c5764e 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td @@ -652,7 +652,7 @@ def ROTL64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), [(set GR64:$dst, (rotl GR64:$src, (i32 imm:$amt)))]>; //===----------------------------------------------------------------------===// -// Test instructions (like AND but do not produce any result +// Test instructions (like AND but do not produce any result) // Integer comparisons let Defs = [PSW] in { diff --git a/llvm/lib/Target/SystemZ/SystemZOperands.td b/llvm/lib/Target/SystemZ/SystemZOperands.td index 495a9d5d564..d783050358d 100644 --- a/llvm/lib/Target/SystemZ/SystemZOperands.td +++ b/llvm/lib/Target/SystemZ/SystemZOperands.td @@ -252,7 +252,7 @@ def s32imm64 : Operand<i64> { // riaddr := reg + imm def riaddr32 : Operand<i32>, - ComplexPattern<i32, 2, "SelectAddrRI12", []> { + ComplexPattern<i32, 2, "SelectAddrRI12Only", []> { let PrintMethod = "printRIAddrOperand"; let MIOperandInfo = (ops ADDR32:$base, u12imm:$disp); } |
