diff options
| author | Jim Grosbach <grosbach@apple.com> | 2010-10-13 23:34:31 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-10-13 23:34:31 +0000 |
| commit | 340cd5174b78ef41f74edb42cb3e847c408d05b4 (patch) | |
| tree | 72e38c0724fcf695a93fdde0c9c3750ceaa8d7c0 /llvm/lib | |
| parent | b9386558a7d4c004338561e7ce326a415982865a (diff) | |
| download | bcm5719-llvm-340cd5174b78ef41f74edb42cb3e847c408d05b4.tar.gz bcm5719-llvm-340cd5174b78ef41f74edb42cb3e847c408d05b4.zip | |
A few 80 column fixes.
llvm-svn: 116451
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFastISel.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrNEON.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index a9b31295bc7..46f707ca952 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -1292,7 +1292,7 @@ bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, // Finally update the result. UpdateValueMap(I, ResultReg); } else { - assert(RVLocs.size() == 1 && "Can't handle non-double multi-reg retvals!"); + assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); EVT CopyVT = RVLocs[0].getValVT(); TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index 6f1f5bfa8a8..95458a5d572 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -622,8 +622,8 @@ class VSTQQQQWBPseudo<InstrItinClass itin> // VST1 : Vector Store (multiple single elements) class VST1D<bits<4> op7_4, string Dt> - : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST1, - "vst1", Dt, "\\{$src\\}, $addr", "", []>; + : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), + IIC_VST1, "vst1", Dt, "\\{$src\\}, $addr", "", []>; class VST1Q<bits<4> op7_4, string Dt> : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), IIC_VST1x2, diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index b0acd125645..25b9428f122 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -1207,7 +1207,7 @@ multiclass T2Ipl<bit instr, bit write, string opc> { let Inst{15-12} = 0b1111; } - def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoad_i, opc, + def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoad_i, opc, "\t[$base, $a]", []> { let Inst{31-25} = 0b1111100; let Inst{24} = instr; @@ -1220,7 +1220,7 @@ multiclass T2Ipl<bit instr, bit write, string opc> { let Inst{5-4} = 0b00; // no shift is applied } - def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoad_i, opc, + def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoad_i, opc, "\t[$base, $a, lsl $shamt]", []> { let Inst{31-25} = 0b1111100; let Inst{24} = instr; |
