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| author | Chris Lattner <sabre@nondot.org> | 2006-10-17 21:24:15 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-10-17 21:24:15 +0000 |
| commit | 327b88b102ccdba3362b99ad0c30201b12ee6e56 (patch) | |
| tree | 371370752548b9ef50470628c70157cd119f967b /llvm/lib | |
| parent | 51746a3beeb4e02cb226e7e30ec4f4a7ba9f4ef2 (diff) | |
| download | bcm5719-llvm-327b88b102ccdba3362b99ad0c30201b12ee6e56.tar.gz bcm5719-llvm-327b88b102ccdba3362b99ad0c30201b12ee6e56.zip | |
Fix CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
llvm-svn: 31019
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 997820dd64b..aa6f4ae98c5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3689,7 +3689,7 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We // can only do this if the top bits are known zero. - if (TLI.MaskedValueIsZero(N1, + if (TLI.MaskedValueIsZero(N0, MVT::getIntVTBitMask(N0.getValueType())-1)){ // Okay, get the un-inverted input value. SDOperand Val; |
