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| author | Diogo Sampaio <diogo.sampaio@arm.com> | 2019-11-04 10:41:32 +0000 |
|---|---|---|
| committer | Diogo Sampaio <diogo.sampaio@arm.com> | 2019-11-04 11:33:21 +0000 |
| commit | 3169f0129a682a54cb90996fcb550184af6cdef9 (patch) | |
| tree | 4b5de5cb434218f325feb8f82243a4945afe33e7 /llvm/lib | |
| parent | 51b4b17eb7e6ee2312e3230c7e097df501006360 (diff) | |
| download | bcm5719-llvm-3169f0129a682a54cb90996fcb550184af6cdef9.tar.gz bcm5719-llvm-3169f0129a682a54cb90996fcb550184af6cdef9.zip | |
[FIX] Removed duplicated v4f16 and v8f16 declarations
Reviewers: RKSimon, ostannard
Reviewed By: RKSimon
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69795
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMCallingConv.td | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/llvm/lib/Target/ARM/ARMCallingConv.td b/llvm/lib/Target/ARM/ARMCallingConv.td index 55111f544ff..5df5b56f5af 100644 --- a/llvm/lib/Target/ARM/ARMCallingConv.td +++ b/llvm/lib/Target/ARM/ARMCallingConv.td @@ -20,7 +20,7 @@ def CC_ARM_APCS : CallingConv<[ // Handles byval parameters. CCIfByVal<CCPassByVal<4, 4>>, - + CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, // Pass SwiftSelf in a callee saved register. @@ -80,7 +80,7 @@ def FastCC_ARM_APCS : CallingConv<[ S9, S10, S11, S12, S13, S14, S15]>>, // CPRCs may be allocated to co-processor registers or the stack - they - // may never be allocated to core registers. + // may never be allocated to core registers. CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>, CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>, @@ -165,8 +165,8 @@ def CC_ARM_AAPCS : CallingConv<[ CCIfNest<CCAssignToReg<[R12]>>, // Handle all vector types as either f64 or v2f64. - CCIfType<[v1i64, v2i32, v4i16, v4f16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, - CCIfType<[v2i64, v4i32, v8i16, v8f16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, + CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, + CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, // Pass SwiftSelf in a callee saved register. CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, @@ -182,8 +182,8 @@ def CC_ARM_AAPCS : CallingConv<[ let Entry = 1 in def RetCC_ARM_AAPCS : CallingConv<[ // Handle all vector types as either f64 or v2f64. - CCIfType<[v1i64, v2i32, v4i16, v4f16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, - CCIfType<[v2i64, v4i32, v8i16, v8f16, v8f16,v16i8, v4f32], CCBitConvertToType<v2f64>>, + CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, + CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, // Pass SwiftSelf in a callee saved register. CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, @@ -208,8 +208,8 @@ def CC_ARM_AAPCS_VFP : CallingConv<[ CCIfByVal<CCPassByVal<4, 4>>, // Handle all vector types as either f64 or v2f64. - CCIfType<[v1i64, v2i32, v4i16, v4f16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, - CCIfType<[v2i64, v4i32, v8i16, v8f16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, + CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, + CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, // Pass SwiftSelf in a callee saved register. CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, @@ -230,8 +230,8 @@ def CC_ARM_AAPCS_VFP : CallingConv<[ let Entry = 1 in def RetCC_ARM_AAPCS_VFP : CallingConv<[ // Handle all vector types as either f64 or v2f64. - CCIfType<[v1i64, v2i32, v4i16, v4f16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, - CCIfType<[v2i64, v4i32, v8i16, v8f16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, + CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>, + CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, // Pass SwiftSelf in a callee saved register. CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, |
