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| author | Hans Wennborg <hans@hanshq.net> | 2018-03-26 10:07:51 +0000 |
|---|---|---|
| committer | Hans Wennborg <hans@hanshq.net> | 2018-03-26 10:07:51 +0000 |
| commit | 311b63f13b0873b183f2a7e57eecf0257c7bffa0 (patch) | |
| tree | 3a063a1198c34d6370c0a3edb1ebb8eadbc4149e /llvm/lib | |
| parent | 8840f644b40b4f764ff5cd297d454429a2fd63c5 (diff) | |
| download | bcm5719-llvm-311b63f13b0873b183f2a7e57eecf0257c7bffa0.tar.gz bcm5719-llvm-311b63f13b0873b183f2a7e57eecf0257c7bffa0.zip | |
Revert r328386 "[X86] Fix Windows `i1 zeroext` conventions to use i8 instead of i32"
This broke Chromium (see crbug.com/825748). It looks like mstorsjo's follow-up
patch at D44876 fixes this, but let's revert back to green for now until that's
ready to land.
(Also reverts r328443.)
> Both GCC and MSVC only look at the low byte of a boolean when it is
> passed.
llvm-svn: 328482
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86CallingConv.td | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 6 |
2 files changed, 5 insertions, 15 deletions
diff --git a/llvm/lib/Target/X86/X86CallingConv.td b/llvm/lib/Target/X86/X86CallingConv.td index d2ade2296b9..8d3e33d5703 100644 --- a/llvm/lib/Target/X86/X86CallingConv.td +++ b/llvm/lib/Target/X86/X86CallingConv.td @@ -593,8 +593,8 @@ def CC_X86_Win64_C : CallingConv<[ // FIXME: Handle byval stuff. // FIXME: Handle varargs. - // Promote i1/v1i1 arguments to i8. - CCIfType<[i1, v1i1], CCPromoteToType<i8>>, + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, // The 'nest' parameter, if any, is passed in R10. CCIfNest<CCAssignToReg<[R10]>>, @@ -619,10 +619,6 @@ def CC_X86_Win64_C : CallingConv<[ CCIfType<[x86mmx], CCBitConvertToType<i64>>, // The first 4 integer arguments are passed in integer registers. - CCIfType<[i8 ], CCAssignToRegWithShadow<[CL , DL , R8B , R9B ], - [XMM0, XMM1, XMM2, XMM3]>>, - CCIfType<[i16], CCAssignToRegWithShadow<[CX , DX , R8W , R9W ], - [XMM0, XMM1, XMM2, XMM3]>>, CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ], [XMM0, XMM1, XMM2, XMM3]>>, @@ -851,15 +847,13 @@ def CC_X86_32_MCU : CallingConv<[ ]>; def CC_X86_32_FastCall : CallingConv<[ - // Promote i1 to i8. - CCIfType<[i1], CCPromoteToType<i8>>, + // Promote i1/i8/i16/v1i1 arguments to i32. + CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, // The 'nest' parameter, if any, is passed in EAX. CCIfNest<CCAssignToReg<[EAX]>>, // The first 2 integer arguments are passed in ECX/EDX - CCIfInReg<CCIfType<[ i8], CCAssignToReg<[ CL, DL]>>>, - CCIfInReg<CCIfType<[i16], CCAssignToReg<[ CX, DX]>>>, CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>, // Otherwise, same as everything else. diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 8e9e090263e..242a008d050 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -3034,11 +3034,7 @@ SDValue X86TargetLowering::LowerFormalArguments( getv64i1Argument(VA, ArgLocs[++I], Chain, DAG, dl, Subtarget); } else { const TargetRegisterClass *RC; - if (RegVT == MVT::i8) - RC = &X86::GR8RegClass; - else if (RegVT == MVT::i16) - RC = &X86::GR16RegClass; - else if (RegVT == MVT::i32) + if (RegVT == MVT::i32) RC = &X86::GR32RegClass; else if (Is64Bit && RegVT == MVT::i64) RC = &X86::GR64RegClass; |

