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authorChris Lattner <sabre@nondot.org>2010-11-14 22:03:15 +0000
committerChris Lattner <sabre@nondot.org>2010-11-14 22:03:15 +0000
commit2f9f63af0b6417160284c0db9c56b49e3e45594d (patch)
tree48c4998c5b4f6b996a9aabda6cb02b443757b52f /llvm/lib
parentcfb62874873b3fb252d8e53cf8798821323b33d7 (diff)
downloadbcm5719-llvm-2f9f63af0b6417160284c0db9c56b49e3e45594d.tar.gz
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lower PPC::MFCRpseud when transforming to MC, avoiding calling
the aborting printSpecial() method. This gets us to 8 failures. llvm-svn: 119084
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp13
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td7
2 files changed, 18 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 039bb4dffac..8cd87de66d4 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -554,13 +554,22 @@ void PPCAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo,
///
void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
if (UseInstPrinter) {
+ MCInst TmpInst;
+
// Lower multi-instruction pseudo operations.
switch (MI->getOpcode()) {
default: break;
- // TODO: implement me.
+
+ case PPC::MFCRpseud:
+ // Transform: %R3 = MFCRpseud %CR7
+ // Into: %R3 = MFCR ;; cr7
+ OutStreamer.AddComment(getRegisterName(MI->getOperand(1).getReg()));
+ TmpInst.setOpcode(PPC::MFCR);
+ TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
+ OutStreamer.EmitInstruction(TmpInst);
+ return;
}
- MCInst TmpInst;
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
OutStreamer.EmitInstruction(TmpInst);
return;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index eb100ec7528..a6156c0c339 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1120,9 +1120,16 @@ def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
// As it turns out, in all cases where we currently use this,
// we're only interested in one subregister of it. Represent this in the
// instruction to keep the register allocator from becoming confused.
+//
+// FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
"mfcr $rT ${:comment} $FXM", SprMFCR>,
PPC970_MicroCode, PPC970_Unit_CRU;
+
+def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
+ "mfcr $rT", SprMFCR>,
+ PPC970_MicroCode, PPC970_Unit_CRU;
+
def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
"mfcr $rT, $FXM", SprMFCR>,
PPC970_DGroup_First, PPC970_Unit_CRU;
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