diff options
| author | Craig Topper <craig.topper@gmail.com> | 2016-06-07 07:27:57 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2016-06-07 07:27:57 +0000 |
| commit | 2f90c1fedf142d36862eb479f874f186d0fd05f5 (patch) | |
| tree | cfb143d86d52d5fd6b5127e48a3b3f7e259a343c /llvm/lib | |
| parent | e1cac15feb17578763f2c3d7f1f9547761df6a82 (diff) | |
| download | bcm5719-llvm-2f90c1fedf142d36862eb479f874f186d0fd05f5.tar.gz bcm5719-llvm-2f90c1fedf142d36862eb479f874f186d0fd05f5.zip | |
[AVX512] Allow avx2 and sse41 nontemporal load intrinsics to select EVEX encoded instructions when VLX is enabled.
llvm-svn: 271988
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 20 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 4 |
2 files changed, 13 insertions, 11 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index bd0f47cb300..d83f9f6ff05 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -3252,18 +3252,20 @@ let SchedRW = [WriteLoad] in { SSEPackedInt>, EVEX, T8PD, EVEX_V512, EVEX_CD8<64, CD8VF>; - let Predicates = [HasAVX512, HasVLX] in { + let Predicates = [HasVLX] in { def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst), - (ins i256mem:$src), - "vmovntdqa\t{$src, $dst|$dst, $src}", [], - SSEPackedInt>, EVEX, T8PD, EVEX_V256, - EVEX_CD8<64, CD8VF>; + (ins i256mem:$src), + "vmovntdqa\t{$src, $dst|$dst, $src}", + [(set VR256X:$dst, (int_x86_avx2_movntdqa addr:$src))], + SSEPackedInt>, EVEX, T8PD, EVEX_V256, + EVEX_CD8<64, CD8VF>; def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst), - (ins i128mem:$src), - "vmovntdqa\t{$src, $dst|$dst, $src}", [], - SSEPackedInt>, EVEX, T8PD, EVEX_V128, - EVEX_CD8<64, CD8VF>; + (ins i128mem:$src), + "vmovntdqa\t{$src, $dst|$dst, $src}", + [(set VR128X:$dst, (int_x86_sse41_movntdqa addr:$src))], + SSEPackedInt>, EVEX, T8PD, EVEX_V128, + EVEX_CD8<64, CD8VF>; } } diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 5a5eb2093ff..e7921a7b43c 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -7246,12 +7246,12 @@ let Predicates = [UseSSE41] in { } let SchedRW = [WriteLoad] in { -let Predicates = [HasAVX] in +let Predicates = [HasAVX, NoVLX] in def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>, VEX; -let Predicates = [HasAVX2] in +let Predicates = [HasAVX2, NoVLX] in def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}", [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>, |
