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authorMatt Arsenault <Matthew.Arsenault@amd.com>2019-09-09 15:39:32 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2019-09-09 15:39:32 +0000
commit2dd088ec7d8bf0804fc00e3583cb0bf10ae5c670 (patch)
treebf150d65fcfe8c9197f8d419132c0ea78ddf3b55 /llvm/lib
parent8b76709bac33f7edf0764416b4e5874c29f23e70 (diff)
downloadbcm5719-llvm-2dd088ec7d8bf0804fc00e3583cb0bf10ae5c670.tar.gz
bcm5719-llvm-2dd088ec7d8bf0804fc00e3583cb0bf10ae5c670.zip
AMDGPU/GlobalISel: Use known bits for selection
llvm-svn: 371409
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp11
1 files changed, 3 insertions, 8 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 99fa46eb665..b55ecd6c6c2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -19,6 +19,7 @@
#include "AMDGPUTargetMachine.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIMachineFunctionInfo.h"
+#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
@@ -1564,12 +1565,6 @@ AMDGPUInstructionSelector::selectFlatOffsetSigned(MachineOperand &Root) const {
return selectFlatOffsetImpl<true>(Root);
}
-// FIXME: Implement
-static bool signBitIsZero(const MachineOperand &Op,
- const MachineRegisterInfo &MRI) {
- return false;
-}
-
static bool isStackPtrRelative(const MachinePointerInfo &PtrInfo) {
auto PSV = PtrInfo.V.dyn_cast<const PseudoSourceValue *>();
return PSV && PSV->isStack();
@@ -1630,7 +1625,7 @@ AMDGPUInstructionSelector::selectMUBUFScratchOffen(MachineOperand &Root) const {
RHSDef->getOperand(1).getCImm()->getSExtValue();
if (SIInstrInfo::isLegalMUBUFImmOffset(PossibleOffset) &&
(!STI.privateMemoryResourceIsRangeChecked() ||
- signBitIsZero(LHS, MRI))) {
+ KnownBits->signBitIsZero(LHS.getReg()))) {
if (LHSDef->getOpcode() == AMDGPU::G_FRAME_INDEX)
FI = LHSDef->getOperand(1).getIndex();
else
@@ -1680,7 +1675,7 @@ bool AMDGPUInstructionSelector::isDSOffsetLegal(const MachineRegisterInfo &MRI,
// On Southern Islands instruction with a negative base value and an offset
// don't seem to work.
- return signBitIsZero(Base, MRI);
+ return KnownBits->signBitIsZero(Base.getReg());
}
InstructionSelector::ComplexRendererFns
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