[Sparc] Formatting and commenting changes per review.

Differential Review: http://reviews.llvm.org/rL273108

llvm-svn: 273876

2 files changed, 191 insertions, 185 deletions

diff --git a/llvm/lib/Target/Sparc/LeonPasses.cpp b/llvm/lib/Target/Sparc/LeonPasses.cpp
index 2823b6592d4..c186cae316a 100755
--- a/llvm/lib/Target/Sparc/LeonPasses.cpp
+++ b/llvm/lib/Target/Sparc/LeonPasses.cpp
@@ -11,62 +11,48 @@
 //===----------------------------------------------------------------------===//
 
 #include "LeonPasses.h"
-#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/ISDOpcodes.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/IR/LLVMContext.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/IR/LLVMContext.h"
+#include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
-LEONMachineFunctionPass::LEONMachineFunctionPass(TargetMachine &tm, char& ID) :
-  MachineFunctionPass(ID)
-{
-}
+LEONMachineFunctionPass::LEONMachineFunctionPass(TargetMachine &tm, char &ID)
+    : MachineFunctionPass(ID) {}
 
-LEONMachineFunctionPass::LEONMachineFunctionPass(char& ID) :
-  MachineFunctionPass(ID)
-{
-}
+LEONMachineFunctionPass::LEONMachineFunctionPass(char &ID)
+    : MachineFunctionPass(ID) {}
 
-int LEONMachineFunctionPass::GetRegIndexForOperand(MachineInstr& MI, int OperandIndex)
-{
+int LEONMachineFunctionPass::GetRegIndexForOperand(MachineInstr &MI,
+                                                   int OperandIndex) {
   if (MI.getNumOperands() > 0) {
     if (OperandIndex == LAST_OPERAND) {
       OperandIndex = MI.getNumOperands() - 1;
     }
 
-    if (MI.getNumOperands() > (unsigned) OperandIndex
-        &&
+    if (MI.getNumOperands() > (unsigned)OperandIndex &&
         MI.getOperand(OperandIndex).isReg()) {
-      return (int) MI.getOperand(OperandIndex).getReg();
+      return (int)MI.getOperand(OperandIndex).getReg();
     }
   }
 
   static int NotFoundIndex = -10;
-  // Return a different number each time to avoid any comparisons between the values returned.
+  // Return a different number each time to avoid any comparisons between the
+  // values returned.
   NotFoundIndex -= 10;
   return NotFoundIndex;
 }
 
-void LEONMachineFunctionPass::clearUsedRegisterList()
-{
-  UsedRegisters.clear();
-}
-
-void LEONMachineFunctionPass::markRegisterUsed(int registerIndex)
-{
-  UsedRegisters.push_back(registerIndex);
-}
-
-//finds a new free FP register
-//checks also the AllocatedRegisters vector
-int LEONMachineFunctionPass::getUnusedFPRegister(MachineRegisterInfo& MRI)
-{
-  for (int RegisterIndex = SP::F0 ; RegisterIndex <= SP::F31 ; ++RegisterIndex) {
+// finds a new free FP register
+// checks also the AllocatedRegisters vector
+int LEONMachineFunctionPass::getUnusedFPRegister(MachineRegisterInfo &MRI) {
+  for (int RegisterIndex = SP::F0; RegisterIndex <= SP::F31; ++RegisterIndex) {
     if (!MRI.isPhysRegUsed(RegisterIndex) &&
-        !(std::find(UsedRegisters.begin(), UsedRegisters.end(), RegisterIndex) != UsedRegisters.end())) {
+        !(std::find(UsedRegisters.begin(), UsedRegisters.end(),
+                    RegisterIndex) != UsedRegisters.end())) {
       return RegisterIndex;
     }
   }
@@ -74,43 +60,41 @@ int LEONMachineFunctionPass::getUnusedFPRegister(MachineRegisterInfo& MRI)
   return -1;
 }
 
-
 //*****************************************************************************
 //**** InsertNOPLoad pass
 //*****************************************************************************
-//This pass inserts a NOP after any LD or LDF instruction.
+// This pass fixes the incorrectly working Load instructions that exists for
+// some earlier versions of the LEON processor line. NOP instructions must
+// be inserted after the load instruction to ensure that the Load instruction
+// behaves as expected for these processors.
+//
+// This pass inserts a NOP after any LD or LDF instruction.
 //
 char InsertNOPLoad::ID = 0;
 
-InsertNOPLoad::InsertNOPLoad(TargetMachine &tm) :
-                    LEONMachineFunctionPass(tm, ID)
-{
-}
+InsertNOPLoad::InsertNOPLoad(TargetMachine &tm)
+    : LEONMachineFunctionPass(tm, ID) {}
 
-bool InsertNOPLoad::runOnMachineFunction(MachineFunction& MF)
-{
+bool InsertNOPLoad::runOnMachineFunction(MachineFunction &MF) {
   Subtarget = &MF.getSubtarget<SparcSubtarget>();
-  const TargetInstrInfo& TII = *Subtarget->getInstrInfo();
+  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
   DebugLoc DL = DebugLoc();
 
   bool Modified = false;
   for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
     MachineBasicBlock &MBB = *MFI;
-    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++ MBBI) {
+    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
       MachineInstr &MI = *MBBI;
       unsigned Opcode = MI.getOpcode();
-      if (Opcode >=  SP::LDDArr && Opcode <= SP::LDrr) {
-        //errs() << "Inserting NOP after LD instruction\n";
+      if (Opcode >= SP::LDDArr && Opcode <= SP::LDrr) {
         MachineBasicBlock::iterator NMBBI = std::next(MBBI);
         BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
         Modified = true;
-      }
-      else if (MI.isInlineAsm()) {
+      } else if (MI.isInlineAsm()) {
         // Look for an inline ld or ldf instruction.
         StringRef AsmString =
             MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
         if (AsmString.startswith_lower("ld")) {
-          //errs() << "Inserting NOP after LD instruction\n";
           MachineBasicBlock::iterator NMBBI = std::next(MBBI);
           BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
           Modified = true;
@@ -125,33 +109,31 @@ bool InsertNOPLoad::runOnMachineFunction(MachineFunction& MF)
 //*****************************************************************************
 //**** FixFSMULD pass
 //*****************************************************************************
-//this pass should convert the FSMULD operands to double precision in scratch registers,
-//then calculate the result with the FMULD instruction. Therefore, the pass should replace operations of the form:
-//fsmuld %f20,%f21,%f8
-//with the sequence:
-//fstod %f20,%f0
-//fstod %f21,%f2
-//fmuld %f0,%f2,%f8
+// This pass fixes the incorrectly working FSMULD instruction that exists for
+// some earlier versions of the LEON processor line.
+//
+// The pass should convert the FSMULD operands to double precision in scratch
+// registers, then calculate the result with the FMULD instruction. Therefore,
+// the pass should replace operations of the form:
+// fsmuld %f20,%f21,%f8
+// with the sequence:
+// fstod %f20,%f0
+// fstod %f21,%f2
+// fmuld %f0,%f2,%f8
 //
 char FixFSMULD::ID = 0;
 
-FixFSMULD::FixFSMULD(TargetMachine &tm) :
-                    LEONMachineFunctionPass(tm, ID)
-{
-}
+FixFSMULD::FixFSMULD(TargetMachine &tm) : LEONMachineFunctionPass(tm, ID) {}
 
-bool FixFSMULD::runOnMachineFunction(MachineFunction& MF)
-{
+bool FixFSMULD::runOnMachineFunction(MachineFunction &MF) {
   Subtarget = &MF.getSubtarget<SparcSubtarget>();
-  const TargetInstrInfo& TII = *Subtarget->getInstrInfo();
+  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
   DebugLoc DL = DebugLoc();
 
-  //errs() << "FixFSMULD on function " << MF.getName() << "\n";
-
   bool Modified = false;
   for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
     MachineBasicBlock &MBB = *MFI;
-    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++ MBBI) {
+    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
 
       MachineInstr &MI = *MBBI;
       unsigned Opcode = MI.getOpcode();
@@ -162,27 +144,31 @@ bool FixFSMULD::runOnMachineFunction(MachineFunction& MF)
       int Reg3Index = UNASSIGNED_INDEX;
 
       if (Opcode == SP::FSMULD && MI.getNumOperands() == 3) {
-        //errs() << "Detected FSMULD\n";
-        //take the registers from fsmuld %f20,%f21,%f8
+        // take the registers from fsmuld %f20,%f21,%f8
         Reg1Index = MI.getOperand(0).getReg();
         Reg2Index = MI.getOperand(1).getReg();
         Reg3Index = MI.getOperand(2).getReg();
-      }
-      else if (MI.isInlineAsm()) {
-        StringRef AsmString(
+      } else if (MI.isInlineAsm()) {
+        std::string AsmString(
             MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName());
-        if (AsmString.startswith_lower("fsmuld")) {
-          //errs() << "Detected InlineAsm FSMULD\n";
+        std::string FMULSOpCoode("fsmuld");
+        std::transform(AsmString.begin(), AsmString.end(), AsmString.begin(),
+                       ::tolower);
+        if (AsmString.find(FMULSOpCoode) ==
+            0) { // this is an inline FSMULD instruction
 
           unsigned StartOp = InlineAsm::MIOp_FirstOperand;
 
-          //extracts the registers from the inline assembly instruction
+          // extracts the registers from the inline assembly instruction
           for (unsigned i = StartOp, e = MI.getNumOperands(); i != e; ++i) {
             const MachineOperand &MO = MI.getOperand(i);
             if (MO.isReg()) {
-              if (Reg1Index == UNASSIGNED_INDEX) Reg1Index = MO.getReg();
-              else if (Reg2Index == UNASSIGNED_INDEX) Reg2Index = MO.getReg();
-              else if (Reg3Index == UNASSIGNED_INDEX) Reg3Index = MO.getReg();
+              if (Reg1Index == UNASSIGNED_INDEX)
+                Reg1Index = MO.getReg();
+              else if (Reg2Index == UNASSIGNED_INDEX)
+                Reg2Index = MO.getReg();
+              else if (Reg3Index == UNASSIGNED_INDEX)
+                Reg3Index = MO.getReg();
             }
             if (Reg3Index != UNASSIGNED_INDEX)
               break;
@@ -190,35 +176,38 @@ bool FixFSMULD::runOnMachineFunction(MachineFunction& MF)
         }
       }
 
-      if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX && Reg3Index != UNASSIGNED_INDEX) {
+      if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX &&
+          Reg3Index != UNASSIGNED_INDEX) {
         clearUsedRegisterList();
         MachineBasicBlock::iterator NMBBI = std::next(MBBI);
-        //Whatever Reg3Index is hasn't been used yet, so we need to reserve it.
+        // Whatever Reg3Index is hasn't been used yet, so we need to reserve it.
         markRegisterUsed(Reg3Index);
         const int ScratchReg1Index = getUnusedFPRegister(MF.getRegInfo());
         markRegisterUsed(ScratchReg1Index);
         const int ScratchReg2Index = getUnusedFPRegister(MF.getRegInfo());
         markRegisterUsed(ScratchReg2Index);
 
-        if (ScratchReg1Index == UNASSIGNED_INDEX || ScratchReg2Index == UNASSIGNED_INDEX) {
-          //errs() << "Cannot allocate free scratch registers for the FixFSMULD pass." << "\n";
-        }
-        else {
-          //create fstod %f20,%f0
+        if (ScratchReg1Index == UNASSIGNED_INDEX ||
+            ScratchReg2Index == UNASSIGNED_INDEX) {
+          errs() << "Cannot allocate free scratch registers for the FixFSMULD "
+                    "pass."
+                 << "\n";
+        } else {
+          // create fstod %f20,%f0
           BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
-          .addReg(ScratchReg1Index)
-          .addReg(Reg1Index);
+              .addReg(ScratchReg1Index)
+              .addReg(Reg1Index);
 
-          //create fstod %f21,%f2
+          // create fstod %f21,%f2
           BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
-          .addReg(ScratchReg2Index)
-          .addReg(Reg2Index);
+              .addReg(ScratchReg2Index)
+              .addReg(Reg2Index);
 
-          //create fmuld %f0,%f2,%f8
+          // create fmuld %f0,%f2,%f8
           BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD))
-          .addReg(Reg3Index)
-          .addReg(ScratchReg1Index)
-          .addReg(ScratchReg2Index);
+              .addReg(Reg3Index)
+              .addReg(ScratchReg1Index)
+              .addReg(ScratchReg2Index);
 
           MI.eraseFromParent();
           MBBI = NMBBI;
@@ -232,38 +221,35 @@ bool FixFSMULD::runOnMachineFunction(MachineFunction& MF)
   return Modified;
 }
 
-
 //*****************************************************************************
 //**** ReplaceFMULS pass
 //*****************************************************************************
-//This pass converts the FMULS operands to double precision in scratch registers,
-//then calculates the result with the FMULD instruction.
-//The pass should replace operations of the form:
-//fmuls %f20,%f21,%f8
-//with the sequence:
-//fstod %f20,%f0
-//fstod %f21,%f2
-//fmuld %f0,%f2,%f8
+// This pass fixes the incorrectly working FMULS instruction that exists for
+// some earlier versions of the LEON processor line.
+//
+// This pass converts the FMULS operands to double precision in scratch
+// registers, then calculates the result with the FMULD instruction.
+// The pass should replace operations of the form:
+// fmuls %f20,%f21,%f8
+// with the sequence:
+// fstod %f20,%f0
+// fstod %f21,%f2
+// fmuld %f0,%f2,%f8
 //
 char ReplaceFMULS::ID = 0;
 
-ReplaceFMULS::ReplaceFMULS(TargetMachine &tm) :
-                    LEONMachineFunctionPass(tm, ID)
-{
-}
+ReplaceFMULS::ReplaceFMULS(TargetMachine &tm)
+    : LEONMachineFunctionPass(tm, ID) {}
 
-bool ReplaceFMULS::runOnMachineFunction(MachineFunction& MF)
-{
+bool ReplaceFMULS::runOnMachineFunction(MachineFunction &MF) {
   Subtarget = &MF.getSubtarget<SparcSubtarget>();
-  const TargetInstrInfo& TII = *Subtarget->getInstrInfo();
+  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
   DebugLoc DL = DebugLoc();
 
-  //errs() << "ReplaceFMULS on function " << MF.getName() << "\n";
-
   bool Modified = false;
   for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
     MachineBasicBlock &MBB = *MFI;
-    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++ MBBI) {
+    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
       MachineInstr &MI = *MBBI;
       unsigned Opcode = MI.getOpcode();
 
@@ -273,27 +259,30 @@ bool ReplaceFMULS::runOnMachineFunction(MachineFunction& MF)
       int Reg3Index = UNASSIGNED_INDEX;
 
       if (Opcode == SP::FMULS && MI.getNumOperands() == 3) {
-        //errs() << "Detected FMULS\n";
-        //take the registers from fmuls %f20,%f21,%f8
+        // take the registers from fmuls %f20,%f21,%f8
         Reg1Index = MI.getOperand(0).getReg();
         Reg2Index = MI.getOperand(1).getReg();
         Reg3Index = MI.getOperand(2).getReg();
-      }
-      else if (MI.isInlineAsm()) {
-        StringRef AsmString(
+      } else if (MI.isInlineAsm()) {
+        std::string AsmString(
             MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName());
-        if (AsmString.startswith_lower("fmuls")) {
-          //errs() << "Detected InlineAsm FMULS\n";
-
+        std::string FMULSOpCoode("fmuls");
+        std::transform(AsmString.begin(), AsmString.end(), AsmString.begin(),
+                       ::tolower);
+        if (AsmString.find(FMULSOpCoode) ==
+            0) { // this is an inline FMULS instruction
           unsigned StartOp = InlineAsm::MIOp_FirstOperand;
 
-          //extracts the registers from the inline assembly instruction
+          // extracts the registers from the inline assembly instruction
           for (unsigned i = StartOp, e = MI.getNumOperands(); i != e; ++i) {
             const MachineOperand &MO = MI.getOperand(i);
             if (MO.isReg()) {
-              if (Reg1Index == UNASSIGNED_INDEX) Reg1Index = MO.getReg();
-              else if (Reg2Index == UNASSIGNED_INDEX) Reg2Index = MO.getReg();
-              else if (Reg3Index == UNASSIGNED_INDEX) Reg3Index = MO.getReg();
+              if (Reg1Index == UNASSIGNED_INDEX)
+                Reg1Index = MO.getReg();
+              else if (Reg2Index == UNASSIGNED_INDEX)
+                Reg2Index = MO.getReg();
+              else if (Reg3Index == UNASSIGNED_INDEX)
+                Reg3Index = MO.getReg();
             }
             if (Reg3Index != UNASSIGNED_INDEX)
               break;
@@ -301,35 +290,38 @@ bool ReplaceFMULS::runOnMachineFunction(MachineFunction& MF)
         }
       }
 
-      if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX && Reg3Index != UNASSIGNED_INDEX) {
+      if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX &&
+          Reg3Index != UNASSIGNED_INDEX) {
         clearUsedRegisterList();
         MachineBasicBlock::iterator NMBBI = std::next(MBBI);
-        //Whatever Reg3Index is hasn't been used yet, so we need to reserve it.
+        // Whatever Reg3Index is hasn't been used yet, so we need to reserve it.
         markRegisterUsed(Reg3Index);
         const int ScratchReg1Index = getUnusedFPRegister(MF.getRegInfo());
         markRegisterUsed(ScratchReg1Index);
         const int ScratchReg2Index = getUnusedFPRegister(MF.getRegInfo());
         markRegisterUsed(ScratchReg2Index);
 
-        if (ScratchReg1Index == UNASSIGNED_INDEX || ScratchReg2Index == UNASSIGNED_INDEX) {
-          //errs() << "Cannot allocate free scratch registers for the ReplaceFMULS pass." << "\n";
-        }
-        else {
-          //create fstod %f20,%f0
+        if (ScratchReg1Index == UNASSIGNED_INDEX ||
+            ScratchReg2Index == UNASSIGNED_INDEX) {
+          errs() << "Cannot allocate free scratch registers for the "
+                    "ReplaceFMULS pass."
+                 << "\n";
+        } else {
+          // create fstod %f20,%f0
           BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
-          .addReg(ScratchReg1Index)
-          .addReg(Reg1Index);
+              .addReg(ScratchReg1Index)
+              .addReg(Reg1Index);
 
-          //create fstod %f21,%f2
+          // create fstod %f21,%f2
           BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
-          .addReg(ScratchReg2Index)
-          .addReg(Reg2Index);
+              .addReg(ScratchReg2Index)
+              .addReg(Reg2Index);
 
-          //create fmuld %f0,%f2,%f8
+          // create fmuld %f0,%f2,%f8
           BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD))
-          .addReg(Reg3Index)
-          .addReg(ScratchReg1Index)
-          .addReg(ScratchReg2Index);
+              .addReg(Reg3Index)
+              .addReg(ScratchReg1Index)
+              .addReg(ScratchReg2Index);
 
           MI.eraseFromParent();
           MBBI = NMBBI;
@@ -346,57 +338,63 @@ bool ReplaceFMULS::runOnMachineFunction(MachineFunction& MF)
 //*****************************************************************************
 //**** FixAllFDIVSQRT pass
 //*****************************************************************************
-//This pass implements two fixes:
-// 1) fixing the FSQRTS and FSQRTD instructions;
-// 2) fixing the FDIVS and FDIVD instructions.
+// This pass fixes the incorrectly working FDIVx and FSQRTx instructions that
+// exist for some earlier versions of the LEON processor line. Five NOP
+// instructions need to be inserted after these instructions to ensure the
+// correct result is placed in the destination registers before they are used.
+//
+// This pass implements two fixes:
+//  1) fixing the FSQRTS and FSQRTD instructions.
+//  2) fixing the FDIVS and FDIVD instructions.
+//
+// FSQRTS and FDIVS are converted to FDIVD and FSQRTD respectively earlier in
+// the pipeline when this option is enabled, so this pass needs only to deal
+// with the changes that still need implementing for the "double" versions
+// of these instructions.
 //
 char FixAllFDIVSQRT::ID = 0;
 
-FixAllFDIVSQRT::FixAllFDIVSQRT(TargetMachine &tm) :
-                    LEONMachineFunctionPass(tm, ID)
-{
-}
+FixAllFDIVSQRT::FixAllFDIVSQRT(TargetMachine &tm)
+    : LEONMachineFunctionPass(tm, ID) {}
 
-bool FixAllFDIVSQRT::runOnMachineFunction(MachineFunction& MF)
-{
+bool FixAllFDIVSQRT::runOnMachineFunction(MachineFunction &MF) {
   Subtarget = &MF.getSubtarget<SparcSubtarget>();
-  const TargetInstrInfo& TII = *Subtarget->getInstrInfo();
+  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
   DebugLoc DL = DebugLoc();
 
-  //errs() << "FixAllFDIVSQRT on function " << MF.getName() << "\n";
-
   bool Modified = false;
   for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
     MachineBasicBlock &MBB = *MFI;
-    //MBB.print(errs());
-    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++ MBBI) {
+    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
       MachineInstr &MI = *MBBI;
-      //MI.print(errs());
       unsigned Opcode = MI.getOpcode();
 
       if (MI.isInlineAsm()) {
-        StringRef AsmString(
+        std::string AsmString(
             MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName());
-        if (AsmString.startswith_lower("fsqrtd")) {
-          //errs() << "Detected InlineAsm FSQRTD\n";
+        std::string FSQRTDOpCode("fsqrtd");
+        std::string FDIVDOpCode("fdivd");
+        std::transform(AsmString.begin(), AsmString.end(), AsmString.begin(),
+                       ::tolower);
+        if (AsmString.find(FSQRTDOpCode) ==
+            0) { // this is an inline fsqrts instruction
           Opcode = SP::FSQRTD;
-        } else if (AsmString.startswith_lower("fdivd")) {
-          //errs() << "Detected InlineAsm FDIVD\n";
+        } else if (AsmString.find(FDIVDOpCode) ==
+                   0) { // this is an inline fsqrts instruction
           Opcode = SP::FDIVD;
         }
       }
 
-      // Note: FDIVS and FSQRTS cannot be generated when this erratum fix is switched on
-      // so we don't need to check for them here. They will already have been converted
-      // to FSQRTD or FDIVD earlier in the pipeline.
+      // Note: FDIVS and FSQRTS cannot be generated when this erratum fix is
+      // switched on so we don't need to check for them here. They will
+      // already have been converted to FSQRTD or FDIVD earlier in the
+      // pipeline.
       if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) {
-        //errs() << "Inserting 5 NOPs before FSQRTD,FDIVD.\n";
-        for (int InsertedCount=0; InsertedCount<5; InsertedCount++)
+        for (int InsertedCount = 0; InsertedCount < 5; InsertedCount++)
           BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
 
         MachineBasicBlock::iterator NMBBI = std::next(MBBI);
-        //errs() << "Inserting 28 NOPs after FSQRTD,FDIVD.\n";
-        for (int InsertedCount=0; InsertedCount<28; InsertedCount++)
+        for (int InsertedCount = 0; InsertedCount < 28; InsertedCount++)
           BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
 
         Modified = true;
diff --git a/llvm/lib/Target/Sparc/LeonPasses.h b/llvm/lib/Target/Sparc/LeonPasses.h
index 798f63407e3..f22b470b69b 100755
--- a/llvm/lib/Target/Sparc/LeonPasses.h
+++ b/llvm/lib/Target/Sparc/LeonPasses.h
@@ -13,9 +13,9 @@
 #ifndef LLVM_LIB_TARGET_SPARC_LEON_PASSES_H
 #define LLVM_LIB_TARGET_SPARC_LEON_PASSES_H
 
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/Passes.h"
 
 #include "Sparc.h"
 #include "SparcSubtarget.h"
@@ -27,17 +27,21 @@ protected:
   const SparcSubtarget *Subtarget;
   const int LAST_OPERAND = -1;
 
-  //this vector holds free registers that we allocate in groups for some of the LEON passes
-  std::vector <int> UsedRegisters;
+  // this vector holds free registers that we allocate in groups for some of the
+  // LEON passes
+  std::vector<int> UsedRegisters;
 
 protected:
-  LEONMachineFunctionPass(TargetMachine &tm, char& ID);
-  LEONMachineFunctionPass(char& ID);
+  LEONMachineFunctionPass(TargetMachine &tm, char &ID);
+  LEONMachineFunctionPass(char &ID);
+
+  int GetRegIndexForOperand(MachineInstr &MI, int OperandIndex);
+  void clearUsedRegisterList() { UsedRegisters.clear(); }
 
-  int GetRegIndexForOperand(MachineInstr& MI, int OperandIndex);
-  void clearUsedRegisterList();
-  void markRegisterUsed(int registerIndex);
-  int getUnusedFPRegister(MachineRegisterInfo& MRI);
+  void markRegisterUsed(int registerIndex) {
+    UsedRegisters.push_back(registerIndex);
+  }
+  int getUnusedFPRegister(MachineRegisterInfo &MRI);
 };
 
 class LLVM_LIBRARY_VISIBILITY InsertNOPLoad : public LEONMachineFunctionPass {
@@ -45,10 +49,12 @@ public:
   static char ID;
 
   InsertNOPLoad(TargetMachine &tm);
-  bool runOnMachineFunction(MachineFunction& MF) override;
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
-    return "InsertNOPLoad: Erratum Fix LBR35: insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction";
+    return "InsertNOPLoad: Erratum Fix LBR35: insert a NOP instruction after "
+           "every single-cycle load instruction when the next instruction is "
+           "another load/store instruction";
   }
 };
 
@@ -57,7 +63,7 @@ public:
   static char ID;
 
   FixFSMULD(TargetMachine &tm);
-  bool runOnMachineFunction(MachineFunction& MF) override;
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
     return "FixFSMULD: Erratum Fix LBR31: do not select FSMULD";
@@ -69,10 +75,12 @@ public:
   static char ID;
 
   ReplaceFMULS(TargetMachine &tm);
-  bool runOnMachineFunction(MachineFunction& MF) override;
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
-    return "ReplaceFMULS: Erratum Fix LBR32: replace FMULS instruction with a routine using conversions/double precision operations to replace FMULS";
+    return "ReplaceFMULS: Erratum Fix LBR32: replace FMULS instruction with a "
+           "routine using conversions/double precision operations to replace "
+           "FMULS";
   }
 };
 
@@ -81,12 +89,12 @@ public:
   static char ID;
 
   FixAllFDIVSQRT(TargetMachine &tm);
-  bool runOnMachineFunction(MachineFunction& MF) override;
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
-    return "FixAllFDIVSQRT: Erratum Fix LBR34: fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store";
+    return "FixAllFDIVSQRT: Erratum Fix LBR34: fix FDIVS/FDIVD/FSQRTS/FSQRTD "
+           "instructions with NOPs and floating-point store";
   }
 };
 } // namespace llvm
 
-#endif