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| author | Hal Finkel <hfinkel@anl.gov> | 2014-03-06 00:23:33 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2014-03-06 00:23:33 +0000 |
| commit | 2a9d318e4a247340fb4c4fe1cdefe6fb225e6091 (patch) | |
| tree | e1425b24af7f0b70e36189a43f114dffd1bcb434 /llvm/lib | |
| parent | 7c582545a4ea3e6fafc59173f15bbf2c64c68661 (diff) | |
| download | bcm5719-llvm-2a9d318e4a247340fb4c4fe1cdefe6fb225e6091.tar.gz bcm5719-llvm-2a9d318e4a247340fb4c4fe1cdefe6fb225e6091.zip | |
When using CR bit registers on PPC32, handle the i1 vaarg case
When copying an i1 value into a GPR for a vaarg call, we need to explicitly
zero-extend the i1 value (otherwise an invalid CRBIT -> GPR copy will be
generated).
llvm-svn: 203041
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 05e74fb049f..dce6051b182 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3773,6 +3773,9 @@ PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee, } if (VA.isRegLoc()) { + if (Arg.getValueType() == MVT::i1) + Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg); + seenFloatArg |= VA.getLocVT().isFloatingPoint(); // Put argument in a physical register. RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); |
