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| author | Stepan Dyatkovskiy <stpworld@narod.ru> | 2013-05-08 14:51:27 +0000 |
|---|---|---|
| committer | Stepan Dyatkovskiy <stpworld@narod.ru> | 2013-05-08 14:51:27 +0000 |
| commit | 2703bcaad36340e3d55fe3f9ef00460ab0730ad3 (patch) | |
| tree | 08ebc0cd42e8226f0706df8d4bcc1ea8e40fc597 /llvm/lib | |
| parent | 6f4be19b576fc7eb5f3f573ebedbe2cd4a598ee7 (diff) | |
| download | bcm5719-llvm-2703bcaad36340e3d55fe3f9ef00460ab0730ad3.tar.gz bcm5719-llvm-2703bcaad36340e3d55fe3f9ef00460ab0730ad3.zip | |
For r181148: fixed warning 'enumeral and non-enumeral type in conditional expression'.
llvm-svn: 181437
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 0f7beb1e3b3..fd777323642 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1795,7 +1795,7 @@ ARMTargetLowering::HandleByVal( // else parameter would be splitted between registers and stack, // end register would be r4 in this case. unsigned ByValRegBegin = reg; - unsigned ByValRegEnd = (size < excess) ? reg + size/4 : ARM::R4; + unsigned ByValRegEnd = (size < excess) ? reg + size/4 : (unsigned)ARM::R4; State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd); // Note, first register is allocated in the beginning of function already, // allocate remained amount of registers we need. |
