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| author | Diogo N. Sampaio <diogo.sampaio@arm.com> | 2019-04-23 09:36:39 +0000 |
|---|---|---|
| committer | Diogo N. Sampaio <diogo.sampaio@arm.com> | 2019-04-23 09:36:39 +0000 |
| commit | 2619f399f99573609be11c608f5f20f1dab595f0 (patch) | |
| tree | 57ce478e96dcb52edd7eb6c893e86c9801a2e4a1 /llvm/lib | |
| parent | 545f621a7c76d0a2fc9b2f657c38da8252d2f9cc (diff) | |
| download | bcm5719-llvm-2619f399f99573609be11c608f5f20f1dab595f0.tar.gz bcm5719-llvm-2619f399f99573609be11c608f5f20f1dab595f0.zip | |
[ARM][FIX] Add missing f16.lane.vldN/vstN lowering
Summary:
Add missing D and Q lane VLDSTLane lowering
for fp16 elements.
Reviewers: efriedma, kosarev, SjoerdMeijer, ostannard
Reviewed By: efriedma
Subscribers: javed.absar, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60874
llvm-svn: 358962
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index b9c4317c9cf..cb66d16a194 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -2092,10 +2092,12 @@ void ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating, default: llvm_unreachable("unhandled vld/vst lane type"); // Double-register operations: case MVT::v8i8: OpcodeIndex = 0; break; + case MVT::v4f16: case MVT::v4i16: OpcodeIndex = 1; break; case MVT::v2f32: case MVT::v2i32: OpcodeIndex = 2; break; // Quad-register operations: + case MVT::v8f16: case MVT::v8i16: OpcodeIndex = 0; break; case MVT::v4f32: case MVT::v4i32: OpcodeIndex = 1; break; |
