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authorLauro Ramos Venancio <lauro.venancio@gmail.com>2007-03-20 16:46:44 +0000
committerLauro Ramos Venancio <lauro.venancio@gmail.com>2007-03-20 16:46:44 +0000
commit25878b45f5f2fa6be8cee650432d3b59945da2c4 (patch)
tree11766ee5732c5727dfa68e868d75ba55d31673c3 /llvm/lib
parent76e4fdf879abbc85b7a93897bf8c0cfda7a7a104 (diff)
downloadbcm5719-llvm-25878b45f5f2fa6be8cee650432d3b59945da2c4.tar.gz
bcm5719-llvm-25878b45f5f2fa6be8cee650432d3b59945da2c4.zip
CopyToReg source operand can be a physical register.
llvm-svn: 35213
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp22
1 files changed, 19 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index ca256deeaf7..10a85868d55 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -475,9 +475,25 @@ void ScheduleDAG::EmitNode(SDNode *Node,
else
InReg = getVR(Node->getOperand(2), VRBaseMap);
unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
- if (InReg != DestReg) // Coalesced away the copy?
- MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg,
- RegMap->getRegClass(InReg));
+ if (InReg != DestReg) {// Coalesced away the copy?
+ const TargetRegisterClass *TRC = 0;
+ // Get the target register class
+ if (MRegisterInfo::isVirtualRegister(InReg)) {
+ TRC = RegMap->getRegClass(InReg);
+ } else {
+ // Pick the register class of the right type that contains this
+ // physreg.
+ for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
+ E = MRI->regclass_end(); I != E; ++I)
+ if ((*I)->hasType(Node->getOperand(2).getValueType()) &&
+ (*I)->contains(InReg)) {
+ TRC = *I;
+ break;
+ }
+ assert(TRC && "Couldn't find register class for reg copy!");
+ }
+ MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC);
+ }
break;
}
case ISD::CopyFromReg: {
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