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| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-06-21 17:25:55 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-06-21 17:25:55 +0000 |
| commit | 254d2cf452ac13beb7f32c71d6d5f8d8f1b73ed2 (patch) | |
| tree | 43629d274ff934d72bf2143196bfda2a53f59c94 /llvm/lib | |
| parent | 6292a056a893251a1ee1cdf0ba7172fa338ce63c (diff) | |
| download | bcm5719-llvm-254d2cf452ac13beb7f32c71d6d5f8d8f1b73ed2.tar.gz bcm5719-llvm-254d2cf452ac13beb7f32c71d6d5f8d8f1b73ed2.zip | |
Type::getPrimitiveID() -> getTypeID()
llvm-svn: 14288
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PowerPCISelSimple.cpp | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp b/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp index c9c0e2d870a..af5e16ea4f7 100644 --- a/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp +++ b/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp @@ -39,7 +39,7 @@ namespace { /// size of the type, and whether or not it is floating point. /// static inline TypeClass getClass(const Type *Ty) { - switch (Ty->getPrimitiveID()) { + switch (Ty->getTypeID()) { case Type::SByteTyID: case Type::UByteTyID: return cByte; // Byte operands are class #0 case Type::ShortTyID: @@ -2306,7 +2306,7 @@ void ISel::emitCastOperation(MachineBasicBlock *BB, } unsigned TmpReg = makeAnotherReg(Type::IntTy); - switch (SrcTy->getPrimitiveID()) { + switch (SrcTy->getTypeID()) { case Type::BoolTyID: case Type::SByteTyID: BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg); @@ -2411,7 +2411,7 @@ void ISel::visitVANextInst(VANextInst &I) { unsigned DestReg = getReg(I); unsigned Size; - switch (I.getArgType()->getPrimitiveID()) { + switch (I.getArgType()->getTypeID()) { default: std::cerr << I; assert(0 && "Error: bad type for va_next instruction!"); @@ -2436,7 +2436,7 @@ void ISel::visitVAArgInst(VAArgInst &I) { unsigned VAList = getReg(I.getOperand(0)); unsigned DestReg = getReg(I); - switch (I.getType()->getPrimitiveID()) { + switch (I.getType()->getTypeID()) { default: std::cerr << I; assert(0 && "Error: bad type for va_next instruction!"); diff --git a/llvm/lib/Target/PowerPC/PowerPCISelSimple.cpp b/llvm/lib/Target/PowerPC/PowerPCISelSimple.cpp index c9c0e2d870a..af5e16ea4f7 100644 --- a/llvm/lib/Target/PowerPC/PowerPCISelSimple.cpp +++ b/llvm/lib/Target/PowerPC/PowerPCISelSimple.cpp @@ -39,7 +39,7 @@ namespace { /// size of the type, and whether or not it is floating point. /// static inline TypeClass getClass(const Type *Ty) { - switch (Ty->getPrimitiveID()) { + switch (Ty->getTypeID()) { case Type::SByteTyID: case Type::UByteTyID: return cByte; // Byte operands are class #0 case Type::ShortTyID: @@ -2306,7 +2306,7 @@ void ISel::emitCastOperation(MachineBasicBlock *BB, } unsigned TmpReg = makeAnotherReg(Type::IntTy); - switch (SrcTy->getPrimitiveID()) { + switch (SrcTy->getTypeID()) { case Type::BoolTyID: case Type::SByteTyID: BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg); @@ -2411,7 +2411,7 @@ void ISel::visitVANextInst(VANextInst &I) { unsigned DestReg = getReg(I); unsigned Size; - switch (I.getArgType()->getPrimitiveID()) { + switch (I.getArgType()->getTypeID()) { default: std::cerr << I; assert(0 && "Error: bad type for va_next instruction!"); @@ -2436,7 +2436,7 @@ void ISel::visitVAArgInst(VAArgInst &I) { unsigned VAList = getReg(I.getOperand(0)); unsigned DestReg = getReg(I); - switch (I.getType()->getPrimitiveID()) { + switch (I.getType()->getTypeID()) { default: std::cerr << I; assert(0 && "Error: bad type for va_next instruction!"); |
