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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-07-03 23:33:38 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-07-03 23:33:38 +0000 |
| commit | 24e33d10a0a00603f770e53bd47e3118d27c5f43 (patch) | |
| tree | bfb267b6ad9dfc1ccfcdd68a616574b88e8dbf3b /llvm/lib | |
| parent | 4b8cdd20fb4d1c30b52d22898e5728353c56ffc1 (diff) | |
| download | bcm5719-llvm-24e33d10a0a00603f770e53bd47e3118d27c5f43.tar.gz bcm5719-llvm-24e33d10a0a00603f770e53bd47e3118d27c5f43.zip | |
AMDGPU: Fix indentation of switch
llvm-svn: 241380
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index d56838ec201..9479d233cf9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -2448,17 +2448,18 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N, SDLoc DL(N); switch(N->getOpcode()) { - default: break; - case ISD::MUL: - return performMulCombine(N, DCI); - case AMDGPUISD::MUL_I24: - case AMDGPUISD::MUL_U24: { - SDValue N0 = N->getOperand(0); - SDValue N1 = N->getOperand(1); - simplifyI24(N0, DCI); - simplifyI24(N1, DCI); - return SDValue(); - } + default: + break; + case ISD::MUL: + return performMulCombine(N, DCI); + case AMDGPUISD::MUL_I24: + case AMDGPUISD::MUL_U24: { + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + simplifyI24(N0, DCI); + simplifyI24(N1, DCI); + return SDValue(); + } case ISD::SELECT: { SDValue Cond = N->getOperand(0); if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) { |
