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authorEvan Cheng <evan.cheng@apple.com>2010-04-05 22:21:09 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-04-05 22:21:09 +0000
commit23d16d5b869a65db20f9b73e46dd28885d46cfd5 (patch)
treeef39ac545344ba302bd9227407756a75935e7e89 /llvm/lib
parentadca6082812fa43d1ad4d76d305b80aaa0e8f0d4 (diff)
downloadbcm5719-llvm-23d16d5b869a65db20f9b73e46dd28885d46cfd5.tar.gz
bcm5719-llvm-23d16d5b869a65db20f9b73e46dd28885d46cfd5.zip
Fix ADD32rr_alt instruction encoding bug. Patch by Marius Wachtler.
llvm-svn: 100480
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86InstrInfo.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 65b7ec023d8..940b439d22a 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -2707,7 +2707,7 @@ let isCodeGenOnly = 1 in {
"add{b}\t{$src2, $dst|$dst, $src2}", []>;
def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
"add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
- def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
+ def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
"add{l}\t{$src2, $dst|$dst, $src2}", []>;
}
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