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| author | Craig Topper <craig.topper@intel.com> | 2017-08-14 15:28:47 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-08-14 15:28:47 +0000 |
| commit | 2374de420b501c51596ee7dfff62213a24a45d00 (patch) | |
| tree | fc3db78cc6e6028352512b2ad17aba597f8461b3 /llvm/lib | |
| parent | a1067d9baecd36de4d71b8da95e52f8ef7a00996 (diff) | |
| download | bcm5719-llvm-2374de420b501c51596ee7dfff62213a24a45d00.tar.gz bcm5719-llvm-2374de420b501c51596ee7dfff62213a24a45d00.zip | |
[AVX512] Remove leftover code for when i1 was a legal type from the fast isel load/store code.
Summary:
I don't think we need this code anymore. It only existed because i1 used to be legal.
There's probably more unneeded code in fast isel still.
Reviewers: guyblank, zvi
Reviewed By: guyblank
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36652
llvm-svn: 310843
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86FastISel.cpp | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index 5c1303da83d..928a37a1408 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -329,10 +329,6 @@ bool X86FastISel::X86FastEmitLoad(EVT VT, X86AddressMode &AM, switch (VT.getSimpleVT().SimpleTy) { default: return false; case MVT::i1: - // TODO: Support this properly. - if (Subtarget->hasAVX512()) - return false; - LLVM_FALLTHROUGH; case MVT::i8: Opc = X86::MOV8rm; RC = &X86::GR8RegClass; @@ -510,16 +506,6 @@ bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, case MVT::f80: // No f80 support yet. default: return false; case MVT::i1: { - // In case ValReg is a K register, COPY to a GPR - if (MRI.getRegClass(ValReg) == &X86::VK1RegClass) { - unsigned KValReg = ValReg; - ValReg = createResultReg(&X86::GR32RegClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(TargetOpcode::COPY), ValReg) - .addReg(KValReg); - ValReg = fastEmitInst_extractsubreg(MVT::i8, ValReg, /*Kill=*/true, - X86::sub_8bit); - } // Mask out all but lowest bit. unsigned AndResult = createResultReg(&X86::GR8RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, |
