update a couple of references to SSARegMap.

llvm-svn: 45468

2 files changed, 3 insertions, 3 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index ce0707423e6..f506b3ebfba 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -606,7 +606,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
       SubIdx = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
     }
     
-    // TODO: Add tracking info to SSARegMap of which vregs are subregs
+    // TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs
     // to allow coalescing in the allocator
           
     // If the node is only used by a CopyToReg and the dest reg is a vreg, use
diff --git a/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp b/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
index da8b39fb2d0..d48e1f9bafa 100644
--- a/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -1410,8 +1410,8 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
       (*I)->eraseFromParent();
     }
 
-    // Transfer sub-registers info to SSARegMap now that coalescing information
-    // is complete.
+    // Transfer sub-registers info to MachineRegisterInfo now that coalescing
+    // information is complete.
     RegSubIdxMap.grow(RegInfo.getLastVirtReg()+1);
     while (!SubRegIdxes.empty()) {
       std::pair<unsigned, unsigned> RI = SubRegIdxes.back();