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| author | Chris Lattner <sabre@nondot.org> | 2007-02-15 18:17:56 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2007-02-15 18:17:56 +0000 |
| commit | 21ebae33943d2cf26bd92e70f219bbca9e883b0b (patch) | |
| tree | a862d69c914531dda21b2b7077b1ac8ad6be8067 /llvm/lib | |
| parent | 3dd60a52fdb275ce979750b13a04c17b58ab332c (diff) | |
| download | bcm5719-llvm-21ebae33943d2cf26bd92e70f219bbca9e883b0b.tar.gz bcm5719-llvm-21ebae33943d2cf26bd92e70f219bbca9e883b0b.zip | |
Apply B Scott Michel's patch for PR1184, which improves diagnostics in an
abort case.
llvm-svn: 34306
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index f6e9b2c88b4..868d3335a1a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -302,8 +302,22 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, IIOpNum); assert(RC && "Don't have operand info for this instruction!"); - assert(RegMap->getRegClass(VReg) == RC && - "Register class of operand and regclass of use don't agree!"); + const TargetRegisterClass *VRC = RegMap->getRegClass(VReg); + if (VRC != RC) { + cerr << "Register class of operand and regclass of use don't agree!\n"; +#ifndef NDEBUG + cerr << "Operand = " << IIOpNum << "\n"; + cerr << "Op->Val = "; Op.Val->dump(0); cerr << "\n"; + cerr << "MI = "; MI->print(cerr); + cerr << "VReg = " << VReg << "\n"; + cerr << "VReg RegClass size = " << VRC->getSize() + << ", align = " << VRC->getAlignment() << "\n"; + cerr << "Expected RegClass size = " << RC->getSize() + << ", align = " << RC->getAlignment() << "\n"; +#endif + cerr << "Fatal error, aborting.\n"; + abort(); + } } } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { |
