diff options
author | Chris Lattner <sabre@nondot.org> | 2003-04-26 19:44:35 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2003-04-26 19:44:35 +0000 |
commit | 21d4509d76581828c5e76eabdd15b446503a05d8 (patch) | |
tree | 2b1d69a06ee53623edbe9deb811e6684bec08d18 /llvm/lib | |
parent | e8689fd0526d05d49dceb06cbd8702dc6a78eb43 (diff) | |
download | bcm5719-llvm-21d4509d76581828c5e76eabdd15b446503a05d8.tar.gz bcm5719-llvm-21d4509d76581828c5e76eabdd15b446503a05d8.zip |
IntegerRegSize is always 8 for sparc
llvm-svn: 5961
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 4 | ||||
-rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrSelection.cpp | 5 |
2 files changed, 3 insertions, 6 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index 8bdb0f29669..331fd4608dc 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -441,9 +441,7 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target, uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant); assert(isValidConstant && "Unrecognized constant"); - if (opSize > destSize || - (val->getType()->isSigned() - && destSize < target.getTargetData().getIntegerRegSize())) + if (opSize > destSize || (val->getType()->isSigned() && destSize < 8)) { // operand is larger than dest, // OR both are equal but smaller than the full register size // AND operand is signed, so it may have extra sign bits: diff --git a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp index 50e2fe23d4d..78fb2f20d98 100644 --- a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp @@ -758,8 +758,7 @@ CreateShiftInstructions(const TargetMachine& target, // Value* shiftDest = destVal; unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType()); - if ((shiftOpCode == SLL || shiftOpCode == SLLX) - && opSize < target.getTargetData().getIntegerRegSize()) + if ((shiftOpCode == SLL || shiftOpCode == SLLX) && opSize < 8) { // put SLL result into a temporary shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp"); mcfi.addTemp(shiftDest); @@ -2305,7 +2304,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, .addReg(dest, MOTy::Def); mvec.push_back(M); } - else if (destSize < target.getTargetData().getIntegerRegSize()) + else if (destSize < 8) assert(0 && "Unsupported type size: 32 < size < 64 bits"); } } |