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| author | Petar Avramovic <Petar.Avramovic@rt-rk.com> | 2019-11-15 11:41:25 +0100 |
|---|---|---|
| committer | Petar Avramovic <Petar.Avramovic@rt-rk.com> | 2019-11-15 11:41:25 +0100 |
| commit | 1f559353a7821769c94f03b00cc9c2f65f982d42 (patch) | |
| tree | 5235bf29f843e3eb9525f26d24ef54e842cf7993 /llvm/lib | |
| parent | dda8e9554071164c85ac7b8b14bc5349703deaab (diff) | |
| download | bcm5719-llvm-1f559353a7821769c94f03b00cc9c2f65f982d42.tar.gz bcm5719-llvm-1f559353a7821769c94f03b00cc9c2f65f982d42.zip | |
[MIPS GlobalISel] Select andi, ori and xori
Introduce IntImmLeaf version of PatLeaf immZExt16 for 32-bit immediates.
Change immZExt16 with imm32ZExt16 for andi, ori and xori.
This keeps same behavior for SDAG and allows for GlobalISel selectImpl
to select 'G_CONSTANT imm' + G_AND, G_OR, G_XOR into ANDi, ORi, XORi,
respectively, when 32-bit imm satisfies imm32ZExt16 predicate: zero
extending 16 low bits of imm is equal to imm.
Large number of test changes comes from zero extending of small types
which is transformed into 'and' with bitmask in legalizer.
Differential Revision:https://reviews.llvm.org/D70185
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 9f07c3a914d..833e45eae9f 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1288,6 +1288,9 @@ def immZExt16 : PatLeaf<(imm), [{ else return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); }], LO16>; +def imm32ZExt16 : IntImmLeaf<i32, [{ + return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue(); +}]>; // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). def immSExt32Low16Zero : PatLeaf<(imm), [{ @@ -2063,13 +2066,13 @@ let AdditionalPredicates = [NotInMicroMips] in { ADDI_FM<0x9>, IsAsCheapAsAMove, ISA_MIPS1; def ANDi : MMRel, StdMMR6Rel, - ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>, + ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, imm32ZExt16, and>, ADDI_FM<0xc>, ISA_MIPS1; def ORi : MMRel, StdMMR6Rel, - ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>, + ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, imm32ZExt16, or>, ADDI_FM<0xd>, ISA_MIPS1; def XORi : MMRel, StdMMR6Rel, - ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>, + ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, imm32ZExt16, xor>, ADDI_FM<0xe>, ISA_MIPS1; def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6; |
