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authorCullen Rhodes <cullen.rhodes@arm.com>2019-06-07 08:46:56 +0000
committerCullen Rhodes <cullen.rhodes@arm.com>2019-06-07 08:46:56 +0000
commit1f0d25124498a13019a93832898ff20b28d51303 (patch)
tree726c8fec42715506e9112812d73935890438151a /llvm/lib
parentf7305484841f09dbcacff326730dc3d62addead4 (diff)
downloadbcm5719-llvm-1f0d25124498a13019a93832898ff20b28d51303.tar.gz
bcm5719-llvm-1f0d25124498a13019a93832898ff20b28d51303.zip
[AArch64][AsmParser] error on unexpected SVE predicate type suffix
Summary: This patch fixes a bug in the assembler that permitted a type suffix on predicate registers when not expected. For instance, the following was previously valid: faddv h0, p0.q, z1.h This bug was present in all SVE instructions containing predicates with no type suffix and no predication form qualifier, i.e. /z or /m. The latter instructions are already caught with an appropiate error message by the assembler, e.g.: .text <stdin>:1:13: error: not expecting size suffix cmpne p1.s, p0.b/z, z2.s, 0 ^ A similar issue for SVE vector registers was fixed in: https://reviews.llvm.org/D59636 Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62942 llvm-svn: 362780
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp3
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index a51eb24cbb5..0973d2bd960 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1081,8 +1081,7 @@ public:
if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateVector)
return DiagnosticPredicateTy::NoMatch;
- if (isSVEVectorReg<Class>() &&
- (ElementWidth == 0 || Reg.ElementWidth == ElementWidth))
+ if (isSVEVectorReg<Class>() && (Reg.ElementWidth == ElementWidth))
return DiagnosticPredicateTy::Match;
return DiagnosticPredicateTy::NearMatch;
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