diff options
| author | Sanjiv Gupta <sanjiv.gupta@microchip.com> | 2009-01-18 18:25:27 +0000 |
|---|---|---|
| committer | Sanjiv Gupta <sanjiv.gupta@microchip.com> | 2009-01-18 18:25:27 +0000 |
| commit | 1d2fc787a98f2e97d99b78076345775bc090d68e (patch) | |
| tree | 6b57b26c17f356c42311e8c2ecd4572e2bb90f77 /llvm/lib | |
| parent | c2edafbdff787c16eff07954182b58e81914c39e (diff) | |
| download | bcm5719-llvm-1d2fc787a98f2e97d99b78076345775bc090d68e.tar.gz bcm5719-llvm-1d2fc787a98f2e97d99b78076345775bc090d68e.zip | |
Few targets like PIC16 wants libcall generation for illegal type i16.
llvm-svn: 62467
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 16 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 4 |
2 files changed, 16 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 45df410ae2c..d84cd62b68e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -1586,7 +1586,9 @@ void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, // If nothing else, we can make a libcall. RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; - if (VT == MVT::i32) + if (VT == MVT::i16) + LC = RTLIB::MUL_I16; + else if (VT == MVT::i32) LC = RTLIB::MUL_I32; else if (VT == MVT::i64) LC = RTLIB::MUL_I64; @@ -1662,7 +1664,9 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, bool isSigned; if (N->getOpcode() == ISD::SHL) { isSigned = false; /*sign irrelevant*/ - if (VT == MVT::i32) + if (VT == MVT::i16) + LC = RTLIB::SHL_I16; + else if (VT == MVT::i32) LC = RTLIB::SHL_I32; else if (VT == MVT::i64) LC = RTLIB::SHL_I64; @@ -1670,7 +1674,9 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, LC = RTLIB::SHL_I128; } else if (N->getOpcode() == ISD::SRL) { isSigned = false; - if (VT == MVT::i32) + if (VT == MVT::i16) + LC = RTLIB::SRL_I16; + else if (VT == MVT::i32) LC = RTLIB::SRL_I32; else if (VT == MVT::i64) LC = RTLIB::SRL_I64; @@ -1679,7 +1685,9 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, } else { assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); isSigned = true; - if (VT == MVT::i32) + if (VT == MVT::i16) + LC = RTLIB::SRA_I16; + else if (VT == MVT::i32) LC = RTLIB::SRA_I32; else if (VT == MVT::i64) LC = RTLIB::SRA_I64; diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 41b43d91671..364a12177ff 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -29,15 +29,19 @@ using namespace llvm; /// InitLibcallNames - Set default libcall names. /// static void InitLibcallNames(const char **Names) { + Names[RTLIB::SHL_I16] = "__ashli16"; Names[RTLIB::SHL_I32] = "__ashlsi3"; Names[RTLIB::SHL_I64] = "__ashldi3"; Names[RTLIB::SHL_I128] = "__ashlti3"; + Names[RTLIB::SRL_I16] = "__lshri16"; Names[RTLIB::SRL_I32] = "__lshrsi3"; Names[RTLIB::SRL_I64] = "__lshrdi3"; Names[RTLIB::SRL_I128] = "__lshrti3"; + Names[RTLIB::SRA_I16] = "__ashri16"; Names[RTLIB::SRA_I32] = "__ashrsi3"; Names[RTLIB::SRA_I64] = "__ashrdi3"; Names[RTLIB::SRA_I128] = "__ashrti3"; + Names[RTLIB::MUL_I16] = "__muli16"; Names[RTLIB::MUL_I32] = "__mulsi3"; Names[RTLIB::MUL_I64] = "__muldi3"; Names[RTLIB::MUL_I128] = "__multi3"; |
