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| author | Robert Khasanov <rob.khasanov@gmail.com> | 2014-10-28 18:22:41 +0000 |
|---|---|---|
| committer | Robert Khasanov <rob.khasanov@gmail.com> | 2014-10-28 18:22:41 +0000 |
| commit | 1cf354c92f560d6fd9bf1265b7c235a22f721db1 (patch) | |
| tree | ce25d31a6d6a372cf4e387682d64458e3cf6d55f /llvm/lib | |
| parent | acb7e25d5f29fcc83fd47d514764c27daea115d1 (diff) | |
| download | bcm5719-llvm-1cf354c92f560d6fd9bf1265b7c235a22f721db1.tar.gz bcm5719-llvm-1cf354c92f560d6fd9bf1265b7c235a22f721db1.zip | |
[AVX512] Fix VSQRT packed instructions internal names.
No functional change
llvm-svn: 220808
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 8 |
2 files changed, 9 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 3fd18de6537..6bc653f5bda 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -4275,16 +4275,16 @@ def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src), multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode, X86VectorVTInfo _>{ - defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), + defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst), (ins _.RC:$src), OpcodeStr, "$src", "$src", (_.FloatVT (OpNode _.RC:$src))>, EVEX; let mayLoad = 1 in { - defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), + defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), (ins _.MemOp:$src), OpcodeStr, "$src", "$src", (OpNode (_.FloatVT (bitconvert (_.LdFrag addr:$src))))>, EVEX; - defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), + defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst), (ins _.ScalarMemOp:$src), OpcodeStr, "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr, (OpNode (_.FloatVT @@ -4388,10 +4388,10 @@ defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt", let Predicates = [HasAVX512] in { def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1), (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)), - (VSQRTPSZrr VR512:$src1)>; + (VSQRTPSZr VR512:$src1)>; def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1), (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)), - (VSQRTPDZrr VR512:$src1)>; + (VSQRTPDZr VR512:$src1)>; def : Pat<(f32 (fsqrt FR32X:$src)), (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>; diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index b5cbee566f2..e95e18b5512 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -5468,10 +5468,10 @@ bool X86InstrInfo::isHighLatencyDef(int opc) const { case X86::VSQRTSSm: case X86::VSQRTSSm_Int: case X86::VSQRTSSr: - case X86::VSQRTPDZrm: - case X86::VSQRTPDZrr: - case X86::VSQRTPSZrm: - case X86::VSQRTPSZrr: + case X86::VSQRTPDZm: + case X86::VSQRTPDZr: + case X86::VSQRTPSZm: + case X86::VSQRTPSZr: case X86::VSQRTSDZm: case X86::VSQRTSDZm_Int: case X86::VSQRTSDZr: |
