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| author | David Majnemer <david.majnemer@gmail.com> | 2016-06-28 16:04:46 +0000 |
|---|---|---|
| committer | David Majnemer <david.majnemer@gmail.com> | 2016-06-28 16:04:46 +0000 |
| commit | 1c7d532cde3117a21ade6c5501e6bcf87d7555eb (patch) | |
| tree | 5bff15b270436349446e002cf335127911ac1051 /llvm/lib | |
| parent | 5ac8f5c379f6b56d64a11e0c469356ceb3443b4d (diff) | |
| download | bcm5719-llvm-1c7d532cde3117a21ade6c5501e6bcf87d7555eb.tar.gz bcm5719-llvm-1c7d532cde3117a21ade6c5501e6bcf87d7555eb.zip | |
[X86] Make WRPKRU/RDPKRU pass -verify-machineinstrs
The original implementation attempted to zero registers using
XOR %foo, %foo. This is problematic because it constitutes a
read-modify-write of a register which might not be defined.
Instead, use MOV32r0 to avoid these problems; expandPostRAPseudo does
the right thing here.
llvm-svn: 274024
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0c969c93c61..859c27afe44 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -22547,13 +22547,11 @@ static MachineBasicBlock *emitWRPKRU(MachineInstr *MI, MachineBasicBlock *BB, BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) .addReg(MI->getOperand(0).getReg()); // insert zero to ECX - BuildMI(*BB, MI, dl, TII->get(X86::XOR32rr), X86::ECX) - .addReg(X86::ECX) - .addReg(X86::ECX); + BuildMI(*BB, MI, dl, TII->get(X86::MOV32r0), X86::ECX); + // insert zero to EDX - BuildMI(*BB, MI, dl, TII->get(X86::XOR32rr), X86::EDX) - .addReg(X86::EDX) - .addReg(X86::EDX); + BuildMI(*BB, MI, dl, TII->get(X86::MOV32r0), X86::EDX); + // insert WRPKRU instruction BuildMI(*BB, MI, dl, TII->get(X86::WRPKRUr)); @@ -22567,9 +22565,8 @@ static MachineBasicBlock *emitRDPKRU(MachineInstr *MI, MachineBasicBlock *BB, const TargetInstrInfo *TII = Subtarget.getInstrInfo(); // insert zero to ECX - BuildMI(*BB, MI, dl, TII->get(X86::XOR32rr), X86::ECX) - .addReg(X86::ECX) - .addReg(X86::ECX); + BuildMI(*BB, MI, dl, TII->get(X86::MOV32r0), X86::ECX); + // insert RDPKRU instruction BuildMI(*BB, MI, dl, TII->get(X86::RDPKRUr)); BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) |
