[AVX512] In some cases KORTEST instruction may be used instead of ZEXT + TEST sequence.

Differential Revision: http://reviews.llvm.org/D23490

llvm-svn: 279960

2 files changed, 23 insertions, 5 deletions

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index ca9855e6ec9..dc36d0d1199 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -14900,15 +14900,29 @@ static SDValue EmitKTEST(SDValue Op, SelectionDAG &DAG,
   return SDValue();
 }
 
-/// Emit nodes that will be selected as "test Op0,Op0", or something
-/// equivalent.
-SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, const SDLoc &dl,
-                                    SelectionDAG &DAG) const {
-  if (Op.getValueType() == MVT::i1) {
+static SDValue EmitTEST_i1(SDValue Op, SelectionDAG &DAG, const SDLoc &dl) {
+
+  // Most probably the value is in GPR, use ZEXT + CMP.
+  if(Op.getOpcode() == ISD::TRUNCATE ||
+     Op.getOpcode() == ISD::LOAD ||
+     Op.getOpcode() == ISD::CopyFromReg) {
     SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
     return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
                        DAG.getConstant(0, dl, MVT::i8));
   }
+
+  // Create cmp i1 that should be mapped to KORTEST.
+  return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
+                     DAG.getConstant(0, dl, MVT::i8));
+}
+
+/// Emit nodes that will be selected as "test Op0,Op0", or something
+/// equivalent.
+SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, const SDLoc &dl,
+                                    SelectionDAG &DAG) const {
+  if (Op.getValueType() == MVT::i1)
+    return EmitTEST_i1(Op, DAG, dl);
+
   // CF and OF aren't always set the way we want. Determine which
   // of these we need.
   bool NeedCF = false;
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 0e2eef7cfb9..21736b6c55b 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -2476,6 +2476,10 @@ multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
 defm KTEST   : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
 
+def : Pat<(X86cmp VK1:$src, 0),
+          (KORTESTWrr (COPY_TO_REGCLASS VK1:$src, VK16),
+                      (COPY_TO_REGCLASS VK1:$src, VK16))>, Requires<[HasAVX512]>;
+
 // Mask shift
 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
                              SDNode OpNode> {