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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-11-09 21:22:13 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-11-09 21:22:13 +0000 |
| commit | 1938482bfad037ec4e16ec4f2d8b68d54f6facbf (patch) | |
| tree | 0a67c3d6747a11f3a565cf8684a14d6c71a91b53 /llvm/lib | |
| parent | 2f70bcdb94d46895777abe1673bba10b8e174b2e (diff) | |
| download | bcm5719-llvm-1938482bfad037ec4e16ec4f2d8b68d54f6facbf.tar.gz bcm5719-llvm-1938482bfad037ec4e16ec4f2d8b68d54f6facbf.zip | |
AVX2: Add patterns for variable shift operations
llvm-svn: 144212
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 28 |
2 files changed, 40 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index c34f225dc53..93f7de89de2 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1052,6 +1052,18 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::MUL, MVT::v16i16, Legal); setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); + + setOperationAction(ISD::SHL, MVT::v4i32, Legal); + setOperationAction(ISD::SHL, MVT::v2i64, Legal); + setOperationAction(ISD::SRL, MVT::v4i32, Legal); + setOperationAction(ISD::SRL, MVT::v2i64, Legal); + setOperationAction(ISD::SRA, MVT::v4i32, Legal); + + setOperationAction(ISD::SHL, MVT::v8i32, Legal); + setOperationAction(ISD::SHL, MVT::v4i64, Legal); + setOperationAction(ISD::SRL, MVT::v8i32, Legal); + setOperationAction(ISD::SRL, MVT::v4i64, Legal); + setOperationAction(ISD::SRA, MVT::v8i32, Legal); // Don't lower v32i8 because there is no 128-bit byte mul } else { setOperationAction(ISD::ADD, MVT::v4i64, Custom); diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 068e223e59e..ff4f749168d 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -7689,3 +7689,31 @@ defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", memopv2i64, memopv4i64, VEX_W; defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", memopv4i32, memopv8i32, int_x86_avx2_psrav_d, int_x86_avx2_psrav_d_256>; + + +let Predicates = [HasAVX2] in { + def : Pat<(v4i32 (shl (v4i32 VR128:$src1), (v4i32 VR128:$src2))), + (VPSLLVDrr VR128:$src1, VR128:$src2)>; + def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (v2i64 VR128:$src2))), + (VPSLLVQrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4i32 (srl (v4i32 VR128:$src1), (v4i32 VR128:$src2))), + (VPSRLVDrr VR128:$src1, VR128:$src2)>; + def : Pat<(v2i64 (srl (v2i64 VR128:$src1), (v2i64 VR128:$src2))), + (VPSRLVQrr VR128:$src1, VR128:$src2)>; + def : Pat<(v4i32 (sra (v4i32 VR128:$src1), (v4i32 VR128:$src2))), + (VPSRAVDrr VR128:$src1, VR128:$src2)>; + + def : Pat<(v8i32 (shl (v8i32 VR256:$src1), (v8i32 VR256:$src2))), + (VPSLLVDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (v4i64 VR256:$src2))), + (VPSLLVQYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (srl (v8i32 VR256:$src1), (v8i32 VR256:$src2))), + (VPSRLVDYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v4i64 (srl (v4i64 VR256:$src1), (v4i64 VR256:$src2))), + (VPSRLVQYrr VR256:$src1, VR256:$src2)>; + def : Pat<(v8i32 (sra (v8i32 VR256:$src1), (v8i32 VR256:$src2))), + (VPSRAVDYrr VR256:$src1, VR256:$src2)>; +} + + + |
