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authorBob Wilson <bob.wilson@apple.com>2010-07-08 17:45:26 +0000
committerBob Wilson <bob.wilson@apple.com>2010-07-08 17:45:26 +0000
commit181e5af248438fd127612b72b3bf6d6ccc85b32d (patch)
tree17858f7211a7205305d57b7f7698bd0191012818 /llvm/lib
parentdf69264765f84999ff2b3352854820071c211443 (diff)
downloadbcm5719-llvm-181e5af248438fd127612b72b3bf6d6ccc85b32d.tar.gz
bcm5719-llvm-181e5af248438fd127612b72b3bf6d6ccc85b32d.zip
The NEONPreAllocPass should never have to assign fixed registers anymore.
This pass can go away entirely soon. llvm-svn: 107892
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/NEONPreAllocPass.cpp35
1 files changed, 1 insertions, 34 deletions
diff --git a/llvm/lib/Target/ARM/NEONPreAllocPass.cpp b/llvm/lib/Target/ARM/NEONPreAllocPass.cpp
index e33a504745d..f67717cdd56 100644
--- a/llvm/lib/Target/ARM/NEONPreAllocPass.cpp
+++ b/llvm/lib/Target/ARM/NEONPreAllocPass.cpp
@@ -468,40 +468,7 @@ bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) {
continue;
if (FormsRegSequence(MI, FirstOpnd, NumRegs, Offset, Stride))
continue;
-
- MachineBasicBlock::iterator NextI = llvm::next(MBBI);
- for (unsigned R = 0; R < NumRegs; ++R) {
- MachineOperand &MO = MI->getOperand(FirstOpnd + R);
- assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
- unsigned VirtReg = MO.getReg();
- assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
- "expected a virtual register");
-
- // For now, just assign a fixed set of adjacent registers.
- // This leaves plenty of room for future improvements.
- static const unsigned NEONDRegs[] = {
- ARM::D0, ARM::D1, ARM::D2, ARM::D3,
- ARM::D4, ARM::D5, ARM::D6, ARM::D7
- };
- MO.setReg(NEONDRegs[Offset + R * Stride]);
-
- if (MO.isUse()) {
- // Insert a copy from VirtReg.
- TII->copyRegToReg(MBB, MBBI, MO.getReg(), VirtReg,
- ARM::DPRRegisterClass, ARM::DPRRegisterClass,
- DebugLoc());
- if (MO.isKill()) {
- MachineInstr *CopyMI = prior(MBBI);
- CopyMI->findRegisterUseOperand(VirtReg)->setIsKill();
- }
- MO.setIsKill();
- } else if (MO.isDef() && !MO.isDead()) {
- // Add a copy to VirtReg.
- TII->copyRegToReg(MBB, NextI, VirtReg, MO.getReg(),
- ARM::DPRRegisterClass, ARM::DPRRegisterClass,
- DebugLoc());
- }
- }
+ llvm_unreachable("expected a REG_SEQUENCE");
}
return Modified;
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