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| author | Chris Lattner <sabre@nondot.org> | 2002-12-02 21:56:18 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2002-12-02 21:56:18 +0000 |
| commit | 15fbd6166463ba63ebd61c4c239debaba372c778 (patch) | |
| tree | 6c883c16f917384c8840c4d874f390f2e0633aee /llvm/lib | |
| parent | 1207ccdbc1a917f84750b17509996b54bd82c04f (diff) | |
| download | bcm5719-llvm-15fbd6166463ba63ebd61c4c239debaba372c778.tar.gz bcm5719-llvm-15fbd6166463ba63ebd61c4c239debaba372c778.zip | |
More support for machine code emission: raw instructions
llvm-svn: 4872
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/MachineCodeEmitter.cpp | 21 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86CodeEmitter.cpp | 21 |
2 files changed, 30 insertions, 12 deletions
diff --git a/llvm/lib/Target/X86/MachineCodeEmitter.cpp b/llvm/lib/Target/X86/MachineCodeEmitter.cpp index ff6b4c6ce30..a9b0c60acc1 100644 --- a/llvm/lib/Target/X86/MachineCodeEmitter.cpp +++ b/llvm/lib/Target/X86/MachineCodeEmitter.cpp @@ -13,10 +13,12 @@ namespace { struct Emitter : public FunctionPass { - TargetMachine &TM; - MachineCodeEmitter &MCE; + X86TargetMachine &TM; + const X86InstrInfo &II; + MachineCodeEmitter &MCE; - Emitter(TargetMachine &tm, MachineCodeEmitter &mce) : TM(tm), MCE(mce) {} + Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce) + : TM(tm), II(TM.getInstrInfo()), MCE(mce) {} bool runOnFunction(Function &F); @@ -56,14 +58,21 @@ void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { void Emitter::emitInstruction(MachineInstr &MI) { unsigned Opcode = MI.getOpcode(); - const MachineInstrDescriptor &Desc = TM.getInstrInfo().get(Opcode); + const MachineInstrDescriptor &Desc = II.get(Opcode); // Emit instruction prefixes if neccesary if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size... - if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F); // Two-byte opcode prefix + if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F);// Two-byte opcode prefix switch (Desc.TSFlags & X86II::FormMask) { case X86II::RawFrm: - ; + MCE.emitByte(II.getBaseOpcodeFor(Opcode)); + + if (MI.getNumOperands() == 1) { + assert(MI.getOperand(0).getType() == MachineOperand::MO_PCRelativeDisp); + MCE.emitPCRelativeDisp(MI.getOperand(0).getVRegValue()); + } + + break; } } diff --git a/llvm/lib/Target/X86/X86CodeEmitter.cpp b/llvm/lib/Target/X86/X86CodeEmitter.cpp index ff6b4c6ce30..a9b0c60acc1 100644 --- a/llvm/lib/Target/X86/X86CodeEmitter.cpp +++ b/llvm/lib/Target/X86/X86CodeEmitter.cpp @@ -13,10 +13,12 @@ namespace { struct Emitter : public FunctionPass { - TargetMachine &TM; - MachineCodeEmitter &MCE; + X86TargetMachine &TM; + const X86InstrInfo &II; + MachineCodeEmitter &MCE; - Emitter(TargetMachine &tm, MachineCodeEmitter &mce) : TM(tm), MCE(mce) {} + Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce) + : TM(tm), II(TM.getInstrInfo()), MCE(mce) {} bool runOnFunction(Function &F); @@ -56,14 +58,21 @@ void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { void Emitter::emitInstruction(MachineInstr &MI) { unsigned Opcode = MI.getOpcode(); - const MachineInstrDescriptor &Desc = TM.getInstrInfo().get(Opcode); + const MachineInstrDescriptor &Desc = II.get(Opcode); // Emit instruction prefixes if neccesary if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size... - if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F); // Two-byte opcode prefix + if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F);// Two-byte opcode prefix switch (Desc.TSFlags & X86II::FormMask) { case X86II::RawFrm: - ; + MCE.emitByte(II.getBaseOpcodeFor(Opcode)); + + if (MI.getNumOperands() == 1) { + assert(MI.getOperand(0).getType() == MachineOperand::MO_PCRelativeDisp); + MCE.emitPCRelativeDisp(MI.getOperand(0).getVRegValue()); + } + + break; } } |
