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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-06-29 16:56:09 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-06-29 16:56:09 +0000 |
| commit | 15a2f6d58c97f481dc82130f87d98f76381f5e8b (patch) | |
| tree | 8162a26028597a1f1b5516c9b57ea2c26a10c006 /llvm/lib | |
| parent | 84cfb884e28fce0571e8f04c76f42546df805072 (diff) | |
| download | bcm5719-llvm-15a2f6d58c97f481dc82130f87d98f76381f5e8b.tar.gz bcm5719-llvm-15a2f6d58c97f481dc82130f87d98f76381f5e8b.zip | |
[X86] Lower blended PACKUSes using appropriate types.
When lowering two blended PACKUS, we used to disregard the types
of the PACKUS inputs, indiscriminately generating a v16i8 PACKUS.
This leads to non-selectable things like:
(v16i8 (PACKUS (v4i32 v0), (v4i32 v1)))
Instead, check that the PACKUSes have the same type, and use that
as the final result type.
llvm-svn: 274138
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 859c27afe44..7d6f5c578fb 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -8943,22 +8943,25 @@ static SDValue lowerV2I64VectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, assert(Mask[0] < 2 && "We sort V1 to be the first input."); assert(Mask[1] >= 2 && "We sort V2 to be the second input."); - // If we have a blend of two PACKUS operations an the blend aligns with the - // low and half halves, we can just merge the PACKUS operations. This is - // particularly important as it lets us merge shuffles that this routine itself - // creates. + // If we have a blend of two same-type PACKUS operations and the blend aligns + // with the low and high halves, we can just merge the PACKUS operations. + // This is particularly important as it lets us merge shuffles that this + // routine itself creates. auto GetPackNode = [](SDValue V) { V = peekThroughBitcasts(V); return V.getOpcode() == X86ISD::PACKUS ? V : SDValue(); }; if (SDValue V1Pack = GetPackNode(V1)) - if (SDValue V2Pack = GetPackNode(V2)) - return DAG.getBitcast(MVT::v2i64, - DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, - Mask[0] == 0 ? V1Pack.getOperand(0) - : V1Pack.getOperand(1), - Mask[1] == 2 ? V2Pack.getOperand(0) - : V2Pack.getOperand(1))); + if (SDValue V2Pack = GetPackNode(V2)) { + EVT PackVT = V1Pack.getValueType(); + if (PackVT == V2Pack.getValueType()) + return DAG.getBitcast(MVT::v2i64, + DAG.getNode(X86ISD::PACKUS, DL, PackVT, + Mask[0] == 0 ? V1Pack.getOperand(0) + : V1Pack.getOperand(1), + Mask[1] == 2 ? V2Pack.getOperand(0) + : V2Pack.getOperand(1))); + } // Try to use shift instructions. if (SDValue Shift = lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, |

