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| author | Quentin Colombet <qcolombet@apple.com> | 2016-03-04 23:29:39 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2016-03-04 23:29:39 +0000 |
| commit | 13b524597db556d364c53a56c248d00b3a320889 (patch) | |
| tree | b1285bb8c9602c75cd2f70f1437c71d37d9cdaba /llvm/lib | |
| parent | 216b275994ed7419d66271d489215e9122b19aef (diff) | |
| download | bcm5719-llvm-13b524597db556d364c53a56c248d00b3a320889.tar.gz bcm5719-llvm-13b524597db556d364c53a56c248d00b3a320889.zip | |
[X86] Do not use cmpxchgXXb when we need the base pointer (RBX).
cmpxchgXXb uses RBX as one of its implicit argument. I.e., when
we use that instruction we need to clobber RBX. This is generally
fine, expect when RBX is a reserved register because in that case,
the register allocator will not track its value and will not
save and restore it when interferences occur.
rdar://problem/24851412
llvm-svn: 262759
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 65b8fb88b6d..e85c04e4f7c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -21162,6 +21162,15 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, Results); } case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: { + // If the current function needs the base pointer, RBX, + // we shouldn't use cmpxchg. + // Indeed the lowering of that instruction will clobber + // that register and since RBX will be a reserved register + // the register allocator will not make sure its value will + // be properly saved and restored around this live-range. + const X86RegisterInfo *TRI = Subtarget.getRegisterInfo(); + if (TRI->hasBasePointer(DAG.getMachineFunction())) + return; EVT T = N->getValueType(0); assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); bool Regs64bit = T == MVT::i128; |

