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author | Tom Stellard <thomas.stellard@amd.com> | 2014-08-21 20:40:50 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2014-08-21 20:40:50 +0000 |
commit | 11aa80cc4a41e95a2796df82537d701fc8273e4e (patch) | |
tree | c9779400a8dba60ea870e8d0a06892c9482cc8e7 /llvm/lib | |
parent | 33466a745e6c1ad2bac2bac57b04e5d488b90e69 (diff) | |
download | bcm5719-llvm-11aa80cc4a41e95a2796df82537d701fc8273e4e.tar.gz bcm5719-llvm-11aa80cc4a41e95a2796df82537d701fc8273e4e.zip |
R600/SI: Handle VCC in SIRegisterInfo::getPhysRegSubReg()
This fixes a crash in an ocl conformance test. The test requries
register spilling and is too big to include.
llvm-svn: 216216
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/R600/SIRegisterInfo.cpp | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/SIRegisterInfo.cpp b/llvm/lib/Target/R600/SIRegisterInfo.cpp index 2a9a2ac5dd6..531c5047f50 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.cpp +++ b/llvm/lib/Target/R600/SIRegisterInfo.cpp @@ -148,6 +148,17 @@ const TargetRegisterClass *SIRegisterInfo::getSubRegClass( unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC, unsigned Channel) const { + + switch (Reg) { + case AMDGPU::VCC: + switch(Channel) { + case 0: return AMDGPU::VCC_LO; + case 1: return AMDGPU::VCC_HI; + default: llvm_unreachable("Invalid SubIdx for VCC"); + } + break; + } + unsigned Index = getHWRegIndex(Reg); return SubRC->getRegister(Index + Channel); } |