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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-08-10 19:11:45 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-08-10 19:11:45 +0000 |
| commit | 11587d97beb71f24d584e7e2949d73d07cc07849 (patch) | |
| tree | 4217aded5408235c0dc8db965e54b87fefabce46 /llvm/lib | |
| parent | 57431c9680c8cde0f6cf0e85bed8507b307b080f (diff) | |
| download | bcm5719-llvm-11587d97beb71f24d584e7e2949d73d07cc07849.tar.gz bcm5719-llvm-11587d97beb71f24d584e7e2949d73d07cc07849.zip | |
AMDGPU: Remove unnecessary cast
llvm-svn: 278274
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 348ae86d527..ada0529b0f8 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -904,12 +904,10 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { } case AMDGPU::SI_PC_ADD_REL_OFFSET: { - const SIRegisterInfo *TRI - = static_cast<const SIRegisterInfo *>(ST.getRegisterInfo()); MachineFunction &MF = *MBB.getParent(); unsigned Reg = MI.getOperand(0).getReg(); - unsigned RegLo = TRI->getSubReg(Reg, AMDGPU::sub0); - unsigned RegHi = TRI->getSubReg(Reg, AMDGPU::sub1); + unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0); + unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1); // Create a bundle so these instructions won't be re-ordered by the // post-RA scheduler. |
